Hi,
I have a custom board that I have received four of. It has a T1042 with attached DDR3L memory, 72 bit data bus.
Three of the four boards has functional DDR, the fourth is intermittent failures when SW loads the DDR. I am trying to use the NXP Codewarrior QCVS DDR validation tool but it is failing initialization, and I recall from another project that due to the data bits being swizzled on some of the byte lanes, the DQ mapping registers (DDR_DDR_DQ_MAP0/1/2/3) have to be properly set.
I cannot figure out how to set these from the TRM, as it is minimal in description.
Any more explanation or example you can provide would be great.
Thank you
Trevor
| T1042DQ | Memory DQ |
| 0 | 24 |
| 1 | 26 |
| 2 | 28 |
| 3 | 27 |
| 4 | 25 |
| 5 | 31 |
| 6 | 30 |
| 7 | 29 |
| 8 | 40 |
| 9 | 46 |
| 10 | 42 |
| 11 | 43 |
| 12 | 47 |
| 13 | 41 |
| 14 | 44 |
| 15 | 25 |
| 16 | 16 |
| 17 | 17 |
| 18 | 23 |
| 19 | 19 |
| 20 | 20 |
| 21 | 18 |
| 22 | 22 |
| 23 | 21 |
| 24 | 48 |
| 25 | 52 |
| 26 | 51 |
| 27 | 50 |
| 28 | 49 |
| 29 | 54 |
| 30 | 53 |
| 31 | 55 |
| 32 | 66 |
| 33 | 69 |
| 34 | 68 |
| 35 | 63 |
| 36 | 62 |
| 37 | 67 |
| 38 | 64 |
| 39 | 65 |
| 40 | 8 |
| 41 | 12 |
| 42 | 10 |
| 43 | 9 |
| 44 | 15 |
| 45 | 14 |
| 46 | 13 |
| 47 | 11 |
| 48 | 0 |
| 49 | 3 |
| 50 | 4 |
| 51 | 2 |
| 52 | 1 |
| 53 | 5 |
| 54 | 6 |
| 55 | 7 |
| 56 | 56 |
| 57 | 57 |
| 58 | 62 |
| 59 | 63 |
| 60 | 60 |
| 61 | 61 |
| 62 | 58 |
| 63 | 59 |
| D1_MECC0 | 32 |
| D1_MECC1 | 34 |
| D1_MECC2 | 35 |
| D1_MECC3 | 38 |
| D1_MECC4 | 39 |
| D1_MECC5 | 36 |
| D1_MECC6 | 33 |
| D1_MECC7 | 37 |