CodeWarrior T2080 DDR validation connection issues

[erik_pet]

We have a custom T2080 board that we are attempting to run the RAM validation tool on.  Currently we are booting off of SPI FLASH and get to the point where we can configure the DDR settings using the FSL DDR interactive prompt (enabled with CONFIG_FSL_DDR_INTERACTIVE).  The system is halting after attempting to load the second stage bootloader from ram, hence the desire to run the ram validation tool to correctly configure.  (RAM Used is IS43TR81024BL-125KBLI)  We are running into issues getting connected to the ram validation tool, and CodeWarrior in general using a CWTAP via USB. (CWTAP 900-76173 REV G 16131610). I have described the errors seen along with the setup procedure from a fresh CW workspace.

Setup CW Ram validation:

New clean workspace created within codewarrior.

New > QorIQ Configuration Project

Name t2080RamVal > Next

Processor to be used: T2080 silicon revision 1.1 > Next

Components: DDR Mem controller configuration > Next

1st DDR Controller

Auto Configuration

Discrete DRAM

DDR Controller:

Type - DDR 3L

Data rate - 1600 MT/s

Rank/Chip select - 1

Data bus width - 64 bits

CAS# latency (tCL) - 11 clocks

tRP/tRCD - 11 clocks

ECC enabled

DRAM settings:

DRAM config per device - 1Gb x 8

DRAM speed rating - 1600 MT/s

Finish

Modify Memory Clock setting to 133.3MHz

Launch DDR_mc1:DDR component and open Validation tab.

Target Connections:

Processor - T2080, probe Type - cwtap, JTAG speed - default, Target access - CDDE, cdde path - cdde.exe

Target fails to connect with the following error:

"Target is not ready: 2147500037 (T2080: Secure debug violation)"

CW connection server log:

CCS Windows Release Build 439p0

verbose logging

CCSAPI connection #1 accepted from DESKTOP-6JIJ9V2 at Wed Sep 11 16:51:19 2024

check_min_version(serverh=0,*version)

  api version: 00000004 00000006

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe553d}

cc_version(serverh=0,cc_index=0,index=0,*version)

config_server(config_reg=0,config_data=0x00002B67)

config_chain(serverh=0,cc=0,count=1,*devlist,*generic)

  devlist: t4amp

reset_to_debug(serverh=0,cc=0)

  ERROR(39): Subcore error encountered during multicore operation

parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)

  error: T2080: Secure debug violation

CCSAPI connection #1 from DESKTOP-6JIJ9V2 closed at Wed Sep 11 16:51:20 2024

----------

CCS Windows Release Build 439p0

verbose logging

CCSAPI connection #1 accepted from DESKTOP-6JIJ9V2 at Wed Sep 11 17:08:32 2024

check_min_version(serverh=0,*version)

  api version: 00000004 00000006

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe553d}

cc_version(serverh=0,cc_index=0,index=0,*version)

  ERROR(10): Connection refused

get_remote_user(serverh=0,cc_index=0,*remote_user_hostname,count)

  user:USB

CCSAPI connection #1 from DESKTOP-6JIJ9V2 closed at Wed Sep 11 17:08:38 2024

JTAG Override attempt:

After investigating this issue an attempt was made to override the RCW as multiple sources state this may be caused by missing/incorrect RCW on board. The following tutorial was followed to generate and override with the new RCW:
How to use QorIQ® RCW Override CodeWarrior | NXP Semiconductors

This yields us with either another Secure Debug violation error, or a JTAG configuration error.

We plan on investigating the JTAG configuration issues further tomorrow, and will attempt to work the defined RCW settings into our SPI FLASH RCW. I will follow up with the results.

--------------------------------------

What troubleshooting can be done in order to finalize the connection between the board and CW to allow us to run the RAM validation tool for our board?

Thank you for any help and please let me know if I can provide any further detail on our setup,

Erik

[erik_pet]

We have actually made some progress in getting connected to the board, however we are still experiencing issues with actually running the ram validation tool.

After reworking our RCW to confirm correct setting for our custom board, we had attempted to connect via the CW TAP within the Validation tool.  We had success in getting connected to the board, but only with the JTAG speed kHz set to 2 (lowest possible option) when we expect to be able to run at 33333kHz. We believe this is caused by a signal integrity issue, but for the time being it seems to be okay to run at the lower speed.

Once connected we have attempted to run the test set (Write-Read-Compare, Centering Clock, Read/Write ODT & driver) however we have failed every test with “Configuration error”, and the test result section states “Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware” & “error detect register is not empty, test did not run”.

This led us to believe that the ram is not being turned on during the testing. After scoping the power line to the ram we noticed that it is not receiving power after loading from the JTAG after connecting, thus not actually running the tests.

After modifying the board and confirming the ram receives power during testing, we still received the same result.

Every test has failed with “Configuration error”, and the test result section states “Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware” & “error detect register is not empty, test did not run”.