Changing platform or core clock speed on a T1040D4RDB-PA

[superolmo]

Hello, I am writing code on a T1040D4RDB-PA development board, but the final board will be on a custom CPU that runs at a slower platform and core clock frequency.

Is it possible to change the clock speed on the T1040D4RDB-PA development board?

[superolmo]

Thank you for the answer.

I not sure where to find those fields in memory. I understand that the RCW source cfg_rcw_src is set to the default NOR flash memory, but where in that NOR flash memory are they stored? It seems I need the bank number and base address if I understood correctly.

[Oswalag]

You are correct, RCW source is set to default NOR flash, the mentioned registers are part of the chapter 4.8.8.7 Reset Control Word (RCW) Register Descriptions, please refer to the link below to modify the RCW. 

https://community.nxp.com/t5/T-Series/modify-RCW-file-for-T1024RDB/m-p/1804461?profile.language=en 

[superolmo]

Your last comment gave me what I needed to fill in the blanks, thank you.

I am actually not running Linux on target, so downloading the whole QorIQ Linux SDK is too much effort.

Since I am using VxWorks, all I need is the RCW built repo at https://github.com/nxp-qoriq-yocto-sdk/rcw

I created a new .rcw file from the target specific folder and rebuilt it. That generated the .bin file. Then I went to the UBOOT console and loaded the new binary using TFTP, removed protection from the NOR memory, erased the 0xec00_0000 +20000 location, and finally copied the new binary to it.

[Oswalag]

Hello,

Yes, it is possible.

You have select the core PLL ratio in the fields commented below:

Clock-Related RCW Fields:

SYS_PLL_RAT: Sets the system PLL ratio.

CORE_PLL_RAT: Sets the core PLL ratio.

CLK_SEL: Selects the input reference clock source.

These fields determine how the input clock is multiplied to generate the internal clocks.