Change NOR Flash 16 bit to 32 bit to T4 Series

cancel
Showing results for 
Search instead for 
Did you mean: 

Change NOR Flash 16 bit to 32 bit to T4 Series

Jump to solution
468 Views
vinothkumars
Senior Contributor III

Hi All,

 

   We have a custom board built with T4 Series processor. I changed the NOR flash address from 0xE8000000 - 0xEFFFFFFF to 0xE0000000 - 0xEFFFFFFF and we connected 2 NOR Flash chip in Hardware side.

But, after changed the address of NOR flash memory address the Ethernet is not working in Linux but it's working in u-boot and NAND is working in Linux and not working in u-boot. 

I needs to know, what are the things I want to carry when changed the NOR flash address. And also I provided my changes and please response If I anything I missed.

Currently used Document for NOR Flash,

https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf 

Table 110. NOR Flash Memory Map

Changed location,

  • include/configs/T4240RDB.h

Current,

#define CONFIG_SYS_NOR0_CSPR  (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \

                                                               + 0x8000000) | \

                                                               CSPR_PORT_SIZE_16 | \

                                                               CSPR_MSEL_NOR | \

                                                               CSPR_V)

Modified,

#define CONFIG_SYS_NOR0_CSPR  (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \

                                                               + 0x0000000) | \

                                                               CSPR_PORT_SIZE_32 | \

                                                               CSPR_MSEL_NOR | \

                                                               CSPR_V)

  • arch/powerpc/boot/dts/fsl/t4240rdb.dts,

Current,

ranges = <0 0 0xf 0xe8000000 0x08000000     2 0 0xf 0xff800000 0x00010000      3 0 0xf 0xffdf0000 0x00008000>;    nor@0,0 {    #address-cells = <1>;    #size-cells = <1>;    compatible = "cfi-flash";    reg = <0x0 0x0 0x8000000>;

Modified,

ranges = <0 0 0xf 0xe0000000 0x00000000     2 0 0xf 0xff800000 0x00010000      3 0 0xf 0xffdf0000 0x00008000>;    nor@0,0 {    #address-cells = <1>;    #size-cells = <1>;    compatible = "cfi-flash";    reg = <0x0 0x0 0x0000000>;

Thanks & Regards,

VinothS.

Regards,
Vinothkumar Sekar
Labels (1)
0 Kudos
1 Solution
201 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello vinothkumar s,

Please modify dts as the following

ranges = <0 0 0xf 0xe0000000 0x10000000

For new IFC NOR Flash integration, you also need to modify IFC timing parameters configuration in include/configs/T4240RDB.h. #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80

#define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
                                FTIM0_NOR_TEADC(0x5) | \
                                FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
                                FTIM1_NOR_TRAD_NOR(0x1A) |\
                                FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
                                FTIM2_NOR_TCH(0x4) | \
                                FTIM2_NOR_TWPH(0x0E) | \
                                FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3    0x0

Please refer to https://community.nxp.com/docs/DOC-333350 for details.

Thanks,

Yiping

View solution in original post

0 Kudos
6 Replies
201 Views
vinothkumars
Senior Contributor III

This is the problem with memory map in flashing (changed 16 bit to 32 bit ) and gives unwanted behavior (Ethernet working in u-boot but not in linux as well as NAND working in Linux not in u-boot) . I configured address for FMAN as well as environment variable. There is no root cause, I closed this thread now. I start from working condition and do step by step to resolve this problem.

Regards,

VinothS.

Regards,
Vinothkumar Sekar
0 Kudos
202 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello vinothkumar s,

Please modify dts as the following

ranges = <0 0 0xf 0xe0000000 0x10000000

For new IFC NOR Flash integration, you also need to modify IFC timing parameters configuration in include/configs/T4240RDB.h. #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80

#define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
                                FTIM0_NOR_TEADC(0x5) | \
                                FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
                                FTIM1_NOR_TRAD_NOR(0x1A) |\
                                FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
                                FTIM2_NOR_TCH(0x4) | \
                                FTIM2_NOR_TWPH(0x0E) | \
                                FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3    0x0

Please refer to https://community.nxp.com/docs/DOC-333350 for details.

Thanks,

Yiping

View solution in original post

0 Kudos
201 Views
vinothkumars
Senior Contributor III

Hi yipingwang‌,

RCW is programmed at the beginning of flash, external memory (0xE8000000).
If RCW is hardcoded, stored in Inside processor. So, 0xE8000000 - 0xE801FFFF will free. So, I am planning to flash uImage from 0xE8000000 instead of 0xE8020000.

I configured u-image load address in T4240RDB.h file,

"setenv loadaddr 0xe8000000;"

Is there any other configuration to I need do for changing the uImage start address apart from the board configuration?

Thanks & Regards,

VinothS

Regards,
Vinothkumar Sekar
0 Kudos
201 Views
yipingwang
NXP TechSupport
NXP TechSupport

You could define NOR flash memory map according to your own requirement.

Thanks,

Yiping

0 Kudos
201 Views
vinothkumars
Senior Contributor III

Thank you for your reply.

Regards,

VinothS

Regards,
Vinothkumar Sekar
0 Kudos
201 Views
vinothkumars
Senior Contributor III

Hi Yiping,

Thank you for your reply. I will update soon.

Regards,

VinothS.

Regards,
Vinothkumar Sekar
0 Kudos