Cann't boot T4240QDS-PB board,show "Waiting for D_INIT timeout. Memory may not work."

[leizhihualqytvw]

Hello everyone, I have just started working on a new T4240 QDS board. I have the board failing in the U-boot sequence immediately after detecting the DDR3 ram ("Waiting for D_INIT timeout. Memory may not work."). and the configuration switches and U-Boot booting log as below,and the three 8G DDR3-1866 UDIMM are installed in J23-D2_DIMM#1,

J22-D1_DIMM#1,J200-D3_DIMM#1,however I try to change the SW1 to 0x24,and update the bank4 Uboot to SDK-V1.8 and SDK-V1.9 version,but the issue same before，Any suggestions for this boot issue?thanks!

SW1= 0x17; SW2= 0xfe; SW3= 0x0c; SW4= 0x50; SW5= 0xe2; SW6= 0x0f; SW7= 0xea; SW8= 0xcd; SW9= 0x1f;

U-Boot 2013.01QorIQ-SDK-V1.5 (Dec 15 2013 - 18:54:15)

CPU0:  T4240E, Version: 2.0, (0x82480020)

Core:  E6500, Version: 2.0, (0x80400120)

Clock Configuration:

       CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,

       CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,

       CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667 MHz,

       CCB:733.333 MHz,

       DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz

       FMAN1: 733.333 MHz

       FMAN2: 733.333 MHz

       QMAN:  366.667 MHz

       PME:   533.333 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Reset Configuration Word (RCW):

       00000000: 16070019 18101916 00000000 00000000

       00000010: 04383060 30548c00 ec020000 f5000000

       00000020: 00000000 ee0000ee 00000000 000307fc

       00000030: 00000000 00000000 00000000 00000028

Board: T4240QDS, Sys ID: 0x1e, Sys Ver: 0x14, vBank: 0

FPGA: v6 (T4240QDS_2014_0211_1852), build 547 on Wed Feb 12 00:52:40 2014

SERDES Reference Clocks: SERDES1=125MHz SERDES2=125MHz SERDES3=100MHz SERDES4=100MHz

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM                  

Detected UDIMM                  

Detected UDIMM                  

Waiting for D_INIT timeout. Memory may not work.

22 GiB left unmapped

    DDR: 24 GiB (DDR3, 64-bit, CL=13, ECC on)

       DDR Controller Interleaving Mode: 3-way 4KB

       DDR Chip-Select Interleaving Mode: CS0+CS1

[sonminh]

Hi @leizhihualqytvw , @yipingwang 

Have you been resolve this problem. I had the trouble the same as you with custom board use b4860.

Thanks and brgs

[yipingwang]

Hello leizhihua LQYTVWF,

According to your u-boot log, this error indicates there is hardware or frequency configuration on your target. Please check switch setting and RCW configuration.

Please configure SW7 : 0xFA = 11111010, and use RCW from Linux SDK pre-built ISO, please refer to the attachment.

Have a great day,
Yiping

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[leizhihualqytvw]

Hello,Yiping Wang,

I try it with SW7:0xFA & attach rcw file,and the issue same as before,When I remove the 8G UDIMM in J200-D3_DIMM#1 the Uboot to normal work as below,however When I install the UDIMM to J200-D3_DIMM#1 or J201-D3_DIMM#2 the Uboot will show "Waiting for D_INIT timeout. Memory may not work."

Is not a D3_DIMM memory controller hardware problems？thanks for your feedback.

U-Boot 2013.01QorIQ-SDK-V1.5 (Dec 15 2013 - 18:54:15)

CPU0:  T4240E, Version: 2.0, (0x82480020)

Core:  E6500, Version: 2.0, (0x80400120)

Clock Configuration:

       CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,

       CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,

       CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667 MHz,

       CCB:733.333 MHz,

       DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz

       FMAN1: 733.333 MHz

       FMAN2: 733.333 MHz

       QMAN:  366.667 MHz

       PME:   533.333 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Reset Configuration Word (RCW):

       00000000: 16070019 18101916 00000000 00000000

       00000010: 04383060 30548c00 ec020000 f5000000

       00000020: 00000000 ee0000ee 00000000 000307fc

       00000030: 00000000 00000000 00000000 00000028

Board: T4240QDS, Sys ID: 0x1e, Sys Ver: 0x14, vBank: 0

FPGA: v6 (T4240QDS_2014_0211_1852), build 547 on Wed Feb 12 00:52:40 2014

SERDES Reference Clocks: SERDES1=125MHz SERDES2=125MHz SERDES3=100MHz SERDES4=100MHz

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM                  

Detected UDIMM                  

There is no rank on CS0 for controller 2.

Not all controllers have compatible interleaving mode. All disabled.

14 GiB left unmapped

    DDR: 16 GiB (DDR3, 64-bit, CL=13, ECC on)

       DDR Chip-Select Interleaving Mode: CS0+CS1

VID: Core voltage 1033 mV

Flash: 128 MiB

L2:    2048 KB enabled

enable l2 for cluster 1 fec60000

enable l2 for cluster 2 feca0000

Corenet Platform Cache: 1536 KB enabled

Using SERDES1 Protocol: 1 (0x1)

Using SERDES2 Protocol: 28 (0x1c)

Using SERDES3 Protocol: 6 (0x6)

Using SERDES4 Protocol: 12 (0xc)

SRIO1: enabled

SRIO2: disabled

NAND:  512 MiB

MMC:  FSL_SDHC: 0

EEPROM: CRC mismatch (08bafd4d != 00000000)

PCIe1: Root Complex, no link, regs @ 0xfe240000

PCIe1: Bus 00 - 00

PCIe2: disabled

PCIe3: Root Complex, no link, regs @ 0xfe260000

PCIe3: Bus 01 - 01

PCIe4: disabled

In:    serial

Out:   serial

Err:   serial

Net:   Fman1: Uploading microcode version 106.4.10

Failed to connect

Failed to connect

Fman2: Uploading microcode version 106.4.10

FM1@DTSEC5 [PRIME], FM2@DTSEC5

Hit any key to stop autoboot: 10     0

[yipingwang · Accepted solution]

Hello Lei zhihua,

There should be no problem with software, please refer to my following u-boot log.

Please download T4240QDS Quick start from http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-powe...to check whether you plugged in DDR DIMMs correctly.  In addition, please make sure that you used all the DDR3 DIMMs provided together with t4240QDS board.

If your problem remains, please contact your local FAE to check the hardware for you.

U-Boot 2013.01QorIQ-SDK-V1.5 (Dec 16 2013 - 11:20:16)

CPU0:  T4240E, Version: 2.0, (0x82480020)

Core:  E6500, Version: 2.0, (0x80400120)

Clock Configuration:

      CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,

      CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,

      CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667 MHz,

      CCB:733.333 MHz,

      DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz

      FMAN1: 733.333 MHz

      FMAN2: 733.333 MHz

      QMAN:  366.667 MHz

      PME:  533.333 MHz

L1:    D-cache 32 kB enabled

      I-cache 32 kB enabled

Reset Configuration Word (RCW):

      00000000: 16070019 18101916 00000000 00000000

      00000010: 04383060 30548c00 ec020000 f5000000

      00000020: 00000000 ee0000ee 00000000 000307fc

      00000030: 00000000 00000000 00000000 00000028

Board: T4240QDS, Sys ID: 0x1e, Sys Ver: 0x12, vBank: 4

FPGA: v6 (T4240QDS_2014_0211_1852), build 547 on Wed Feb 12 00:52:40 2014

SERDES Reference Clocks: SERDES1=125MHz SERDES2=125MHz SERDES3=100MHz SERDES4=100MHz

I2C:  ready

SPI:  ready

DRAM:  Initializing....using SPD

Detected UDIMM

Detected UDIMM

Detected UDIMM

22 GiB left unmapped

    DDR: 24 GiB (DDR3, 64-bit, CL=13, ECC on)

      DDR Controller Interleaving Mode: 3-way 4KB

      DDR Chip-Select Interleaving Mode: CS0+CS1

VID: Core voltage 1030 mV

Flash: 128 MiB

L2:    2048 KB enabled

enable l2 for cluster 1 fec60000

enable l2 for cluster 2 feca0000

Corenet Platform Cache: 1536 KB enabled

Using SERDES1 Protocol: 1 (0x1)

Using SERDES2 Protocol: 28 (0x1c)

Using SERDES3 Protocol: 6 (0x6)

Using SERDES4 Protocol: 12 (0xc)

SRIO1: enabled

SRIO2: disabled

NAND:  512 MiB

MMC:  FSL_SDHC: 0

*** Warning - bad CRC, using default environment

EEPROM: NXID v1

PCIe1: Root Complex, no link, regs @ 0xfe240000

PCIe1: Bus 00 - 00

PCIe2: disabled

PCIe3: Root Complex, x1, regs @ 0xfe260000

  02:00.0    - 8086:10d3 - Network controller

PCIe3: Bus 01 - 02

PCIe4: disabled

In:    serial

Out:  serial

Err:  serial

Net:  Fman1: Data at eff40000 is not a firmware

e1000: 68:05:ca:0f:23:a3

      e1000#0

Warning: e1000#0 MAC addresses don't match:

Address in SROM is        68:05:ca:0f:23:a3

Address in environment is  00:e0:0c:00:ae:00

Hit any key to stop autoboot:  0

=>

Have a great day,
Yiping

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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[leizhihualqytvw]

Hello,Yiping Wang,

I double check all configuration with Quick start document,and the issue same as before,Maybe it's hardware issue as you said,i will contact with your local team,however thanks for your kind support!

Lei zhihua