Can the T102x parts be run at 600 or 800MHz core clock?

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Can the T102x parts be run at 600 or 800MHz core clock?

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Larry5335
Contributor IV

To reduce power dissipation, can the T1022 be run at a slower frequency?

i.e. platform clock of 300MHz and the core at 600MHz?

Is there any data or App Notes showing what the expected power at reduced frequencies might be?

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

Yes according to the hardware specifications the T1022 can be run at platform clock of 300MHz and the core at 600MHz (see table 129 in the data sheet rev.2). For example we get that conditions at Platform to SYSCLK PLL ratio =3, Core cluster PLL to SYSCLK ratio = 6 and SYSCLK = 100MHz.

The only available the T1022 data power numbers are in Table 8 of the data sheet. This table shows the power dissipations of the VDD and VDDC supply for various operating platform clock frequencies versus the core and DDR clock frequencies.

Processor module power consumption consists of dynamic portion and leakage portion. The dynamic portion is due to the charging and discharging of the each transistor and its associated capacitance and as result it is proportional to the operation frequency. The leakage portion is due to gate and channel leakage in each transistor. So using data at different frequencies you can try to estimate the power reducing when frequency is decreased.

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

Yes according to the hardware specifications the T1022 can be run at platform clock of 300MHz and the core at 600MHz (see table 129 in the data sheet rev.2). For example we get that conditions at Platform to SYSCLK PLL ratio =3, Core cluster PLL to SYSCLK ratio = 6 and SYSCLK = 100MHz.

The only available the T1022 data power numbers are in Table 8 of the data sheet. This table shows the power dissipations of the VDD and VDDC supply for various operating platform clock frequencies versus the core and DDR clock frequencies.

Processor module power consumption consists of dynamic portion and leakage portion. The dynamic portion is due to the charging and discharging of the each transistor and its associated capacitance and as result it is proportional to the operation frequency. The leakage portion is due to gate and channel leakage in each transistor. So using data at different frequencies you can try to estimate the power reducing when frequency is decreased.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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