CLK for DDR4

[gokulkrishnan]

Hi,

I am using a x8 configuration for DDR4, ie 8 chips for data and one for ECC. Now each chip requires clock. The processor I'm using is T1042. t has two clock outputs ( CLK 0 and 1). So how should I connect them ?? 

Can you let me know about the CKE as well. 

Regards 

Gokul

[r8070z]

Have a great day,

The T1042 supports 32-bit and 64-bit DDR data bus width. I suppose that you are going implement the 64-bit data bus so all 8 chips will be connected to the same chip select MSC0 ( or MCS1). In this case they all ought be connected to the same clock enable CKE0 if MCS0 (or CKE1 if MCS1) is used. The fly-by routing is recommended for address, command, control, and clock signal bus. You may use single differential clock pair for all 8 chips in fly-by mode. Any of the MCKE0/MCKE0 or MCKE1/MCKE1 can be used.

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