CDR Not getting locked on SERDES Lane 7 in T2081

[manishraturi]

Hi We are using T2081 processor on our board. We are using 0xD6 as serdes protocol. On lane 7 which is connected to MAC 6 the CDR is not getting locked constantly.  It is fluctuating sometime up sometime down. How to debug this and what can be the reason of this problem?

Just to add the LANE 1 CDR is constant always and is locked properly

[manishraturi]

When I say CDR is not locked on lane 7 I am talking about the register

Test Control/Status Register 3 - Lane n (SerDesx_LNnTCSR3)

I can see the CDR bit is sometime showing as 1 and sometime as 0.

One more thing I wanted to add here is currently in our system we are validating the below path:

CPU===>BCM Switch

And what I see is, in CPU side though the link is up but the AN is not completed on the PCS layer, below is the reg dump:

=> mm 0xfe4eb034

fe4eb034: 00000001 ? 8000

fe4eb038: 00001140 ? q

=> mm 0xfe4eb034

fe4eb034: 00000001 ? 8001

fe4eb038: 0000000d ? q

=> mm 0xfe4eb034

fe4eb034: 00000001 ? 8014

fe4eb038: 0000000b ? q

U-BOOT LOGS: There are some customized print please ignore them

=====================================================>

U-Boot 2015.01 (May 12 2016 - 16:39:49)

CPU0:  T2081E, Version: 1.1, (0x85390011)

Core:  e6500, Version: 2.0, (0x80400120)

Clock Configuration:

      CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,

      CCB:400  MHz,

      DDR:900  MHz (1800 MT/s data rate) (Asynchronous), IFC:100  MHz

      FMAN1: 400 MHz

      QMAN:  200 MHz

      PME:  400 MHz

L1:    D-cache 32 KiB enabled

      I-cache 32 KiB enabled

Reset Configuration Word (RCW):

      00000000: 0809000f 0f000000 00000000 00000000

      00000010: d6000002 00008000 fc02f000 a1000000

      00000020: 00000000 00000000 00000000 00228001

      00000030: 00000000 5080000d 00000000 00000001

Board: T2081SVC, NOR

SERDES Reference Clocks:

SD1_CLK1=100.00MHZ, SD1_CLK2=100.00MHZ

SD2_CLK1=100.00MHZ, SD2_CLK2=100.00MHZ

I2C:  ready

SPI:  ready

DRAM:  Initializing....using SPD

DINIT is LOW DDR PASSED

2 GiB left unmapped

4 GiB (DDR3, 64-bit, CL=9, ECC on)

VID: Could not find voltage regulator on I2C.

Warning: Adjusting core voltage failed.

Flash: 256 MiB

L2:    2 MiB enabled

Corenet Platform Cache: 512 KiB enabled

Using SERDES1 Protocol: 214 (0xd6)

is_device_disabled: returns 0

PHY_INTERFACE_MODE_SGMII mode for SVC

fman_port_enet_if: port = 0

is_device_disabled: returns 0

PHY_INTERFACE_MODE_SGMII mode for SVC

fman_port_enet_if: port = 1

is_device_disabled: returns 0

is_device_disabled: returns 0

is_device_disabled: returns 0

PHY_INTERFACE_MODE_SGMII mode for SVC

fman_port_enet_if: port = 4

is_device_disabled: returns 0

PHY_INTERFACE_MODE_SGMII mode for SVC

fman_port_enet_if: port = 5

is_device_disabled: returns 0

is_device_disabled: returns 0

PHY_INTERFACE_MODE_SGMII mode for SVC

fman_port_enet_if: port = 7

is_device_disabled: returns 0

is_device_disabled: returns 0

SEC0: RNG instantiated

NAND:  fsl_ifc_chip_init: address did not match any chip selects

0 MiB

MMC:  FSL_SDHC: 0

*** Warning - bad CRC, using default environment

EEPROM: Read failed.

PCIe1: disabled

PCIe2: disabled

PCIe3: Root Complex, x1 gen1, regs @ 0xfe260000

  01:00.0    - 14e4:b150 - Network controller

  01:00.1    - 14e4:b150 - Network controller

PCIe3: Bus 00 - 01

PCIe4: Root Complex, x1 gen1, regs @ 0xfe270000

  03:00.0    - 14e4:b150 - Network controller

  03:00.1    - 14e4:b150 - Network controller

PCIe4: Bus 02 - 03

In:    serial

Out:  serial

Err:  serial

Net:  GPIO = 0xdf1fefbe

BROADCOM INIT

GPIO 1 = 0xdf1fefbe

DEBUG: init.c port = 0x7

fm_info[7].phy_addr = 0x1

SerDes1 protocol 0xd6 is supported on T2081SVC

DEBUG: init.c port = 0x0

DEBUG: init.c port = 0x1

DEBUG: init.c port = 0x2

DEBUG: init.c port = 0x3

DEBUG: init.c port = 0x4

DEBUG: init.c port = 0x5

DEBUG: init.c port = 0x6

DEBUG: init.c port = 0x7

interface SGMII 7 8

DEBUG: init.c port = 0x7

Fman1: Uploading microcode version 106.4.14

index: 1 fm_info size = 10

enabled: 1

memac_set_interface_mode, if_mode = 9002

memac_set_interface_mode, if_status = 2000

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

DEBUG ETH.c: dev->state 0 dev->index 0 dev->name FM1@DTSEC1

index: 1 fm_info size = 10

enabled: 1

memac_set_interface_mode, if_mode = 9002

memac_set_interface_mode, if_status = 2000

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

DEBUG ETH.c: dev->state 0 dev->index 1 dev->name FM1@DTSEC2

index: 1 fm_info size = 10

enabled: 0

index: 1 fm_info size = 10

enabled: 0

index: 1 fm_info size = 10

enabled: 1

memac_set_interface_mode, if_mode = 9002

memac_set_interface_mode, if_status = 2000

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

DEBUG ETH.c: dev->state 0 dev->index 2 dev->name FM1@DTSEC5

index: 1 fm_info size = 10

enabled: 1

memac_set_interface_mode, if_mode = 9002

memac_set_interface_mode, if_status = 2000

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

DEBUG ETH.c: dev->state 0 dev->index 3 dev->name FM1@DTSEC6

index: 1 fm_info size = 10

enabled: 0

index: 1 fm_info size = 10

enabled: 1

memac_set_interface_mode, if_mode = 9002

memac_set_interface_mode, if_status = 2000

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

MDIO WRITE port_addr = 0x0 and dev_addr 0xffffffff

memac_mdio_reset***************

phy_mask 0x2

Calling get PHY ID b 2137719824 A 1 D -1

Calling get PHY ID b 2137719824 A 1 D 0

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg1 = 0xffff

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg2 = 0xffff

phy_mask 0x2

Calling get PHY ID b 2137719824 A 1 D 1

Calling get PHY ID b 2137719824 A 1 D 0

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg1 = 0xffff

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg2 = 0xffff

phy_mask 0x2

Calling get PHY ID b 2137719824 A 1 D 2

Calling get PHY ID b 2137719824 A 1 D 0

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg1 = 0xffff

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg2 = 0xffff

phy_mask 0x2

Calling get PHY ID b 2137719824 A 1 D 3

Calling get PHY ID b 2137719824 A 1 D 0

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg1 = 0xffff

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg2 = 0xffff

phy_mask 0x2

Calling get PHY ID b 2137719824 A 1 D 4

Calling get PHY ID b 2137719824 A 1 D 0

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg1 = 0xffff

MDIO READ port = 0x1 dev 0x0

MDIO READ mdio_ctl = 0x8020

phy_reg2 = 0xffff

Phy 1 not found

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x8020

MDIO WRITE port_addr = 0x1 and dev_addr 0xffffffff

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x8020

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x8021

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x802f

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x8024

MDIO WRITE port_addr = 0x1 and dev_addr 0xffffffff

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x8029

MDIO READ port = 0x1 dev 0xffffffff

MDIO READ mdio_ctl = 0x8020

genphy_restart_aneg 0x1340

MDIO WRITE port_addr = 0x1 and dev_addr 0xffffffff

DEBUG ETH.c: dev->state 0 dev->index 4 dev->name FM1@DTSEC10

index: 1 fm_info size = 10

enabled: 0

index: 1 fm_info size = 10

enabled: 0

fm_info structure now

num: 0

enabled: 1

type: 0

port: 0

rxportid: 8

txportid: 40

compat_offset: 0x4e0000

num: 1

enabled: 1

type: 0

port: 1

rxportid: 9

txportid: 41

compat_offset: 0x4e2000

num: 2

enabled: 0

type: 0

port: 2

rxportid: 10

txportid: 42

compat_offset: 0x4e4000

num: 3

enabled: 0

type: 0

port: 3

rxportid: 11

txportid: 43

compat_offset: 0x4e6000

num: 4

enabled: 1

type: 0

port: 4

rxportid: 12

txportid: 44

compat_offset: 0x4e8000

num: 5

enabled: 1

type: 0

port: 5

rxportid: 13

txportid: 45

compat_offset: 0x4ea000

num: 8

enabled: 0

type: 0

port: 6

rxportid: 16

txportid: 48

compat_offset: 0x4f0000

num: 9

enabled: 1

type: 0

port: 7

rxportid: 17

txportid: 49

compat_offset: 0x4f2000

num: 0

enabled: 0

type: 1

port: 8

rxportid: 16

txportid: 48

compat_offset: 0x4f0000

FM1@DTSEC1DEBUG ETH.C: dev->name FM1@DTSEC1

, FM1@DTSEC2DEBUG ETH.C: dev->name FM1@DTSEC2

, FM1@DTSEC5DEBUG ETH.C: dev->name FM1@DTSEC5

, FM1@DTSEC6DEBUG ETH.C: dev->name FM1@DTSEC6

, FM1@DTSEC10DEBUG ETH.C: dev->name FM1@DTSEC10

GPIO 2= 0xdf1fefbe

BCM

#### Starting Broadcom Initialization. ####

Calling bmd_phy_probe_init

Sridevi:Device is iproc device

Calling shbde_iproc_config_init

Calling shbde_iproc_paxb_init

BCM Device exists 0

calling bmd_reset

calling bmd init

Calling switch init

calling vlan create

calling port vlan set

Done BCM initialization for network-boot

Hit any key to stop autoboot:  0

[ufedor]

1) Please confirm that the BCM Switch is using SGMII @ 1.25 Gbaud.

2) In the provided "PBLorig.bin" there is no workaround for the Erratum "A-007186: SerDes Ring VCO does not maintain lock throughout specified temperature range" - refer to the SDK 1.9

[ufedor]

You wrote:

> CDR is not getting locked constantly

What exactly do you mean?

Please provide dump of the SerDes Module registers, U-Boot booting log and binary image of the RCW being used.