Addressing NOR and NAND Flash on the T2080 using ADM mode 0

[Larry5335]

Customer is using NOR Flash as the primary boot device and then switching over to raw NAND Flash. The driver being used for the NAND requires 4 Ready/Busy hardware lines, 1 for each of the physical Flash components. To set this up in the pin muxing, it looks like IFC_A29:31 become IFC_RB2:4 and these pins are no longer available for NOR Flash addressing.

Is this correct?

What is the largest NOR device that can be addressed assuming IFC_A29:31 are not available and used as RB2:4?

i.e. will using ADM mode 0 with a shift of 3 allow the use of a 2 ** 29 - 512 Mbit NOR Flash or is there some other limit?

[zhylunwen]

hello,Serguei Podiatchev,does t2080 support datasheet figure 13-8?  This is a bug for t2080？

[r8070z]

Yes there is mispint in the T2080 manual figure 13-28. The IFC_A[26] cannot provide the least significant bit of byte address.

[r8070z · Accepted solution]

Have a great day,

Yes IFC_RB2:4 and IFC_A29:31 share 3 pins and if we need for any of IFC_RB2:4 then we lose IFC_A29:31. It is selected in the RCW[IFC_GRP_B].

In the ADM mode 0 (ADM_SHFT_MODE=0) IFC_A29:31 provide 3 least significant address bits irrespective of the ADM_SHFT value. There are not other pins where we can get these 3 lsb. So without IFC_A29:31 we can address 64-bit word only in the ADM mode 0. At the same time we can read 16-bit only through IFC_AD[0:15]. Hence it is not good for parallel NOR flash. I think you should consider using ADM_SHFT_MODE=1 when IFC_AD bus will carry lsbs and IFC_A bus carries the msb.

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