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On T4240RDB Cortina PHY chip doesn’t provide any LED indication function. We should control LED activity by CPLD. So you need figure out what Ethernet link status is. To read link status register is necessary. Cortina PHY is connected to T4240 through XFI interface and this lane uses mEMAC9. First, we looked up T4240 Reference manual and found there is a register which is related to Linking status. XFI PCS MDIO Memory MAP->       0x01 MDIO_XFI_PCS_SR1->                 BIT2 PCS_RX_LNK_STAT We need use internal MDIO bus to read this register. T4240 DPAA document has register information about internal MDIO bus. mEMAC9 base address is 4F_0000h MDIO9 for mEMAC9 base address is 4F_1000h Offset 0x034 ->MDIO Control register Offset 0x038 ->MDIO DATA register Offset 0x3C ->MDIO register address register U-boot Environment: mw 0xfe4f1034 0x3 (Set write command) mw 0xfe4f103c 0x1 (set register address) mw 0xfe4f1034 0x8003 (set read command) md 0xfe4f1038 0x4 (Get read data) mw 0xfe4f1034 0x8003 md 0xfe4f1038 0x4 Linux Environment: (Need install devmem tool first) devmem 0xfe4f1034 32 0x3 (Set write command) devmem 0xfe4f103c 32 0x1 (set register address) devmem 0xfe4f1034 32 0x8003 (set read command) devmem 0xfe4f1038 32 (Get read data)
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For achieving higher throughput using Network Stack QoS, one of the solution is to push the QoS logic from software to hardware. CEETM(Customer-edge egress-traffic management) is DPAA enhancement first appearing in QorIQ T series processors in QMan, it provides hierarchical class based scheduling and traffic shaping. CEETM provides the features dual-rate shaping, weighted CQ scheduling, congestion management, this document introduces these features implementing in USDPAA.
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