MMA8451Q least significant bit

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MMA8451Q least significant bit

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xiao_dong_yu
Contributor I

Hi,

I set the ODR of MMA8451Q to 800 Hz(Set the Register 0x2A to 0x05), then read the values from Register 0x01 to 0x04. I found the least significant bit of X axis and Y axis is always zero (I did not test the Z axis). It mean I always got an even number when the ODR is 800Hz.

When I changed the ODR to 1.56Hz, it became normal. 

Did I configure it wrong?

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Xiaodong,

I have just performed some tests with MMA8451Q on the FRDM-KL25Z board and also found that Bit 2 of OUT_X_LSB/OUT_Y_LSB/OUT_Z_LSB registers remains zero at the ODR of 800Hz. At lower ODRs it changes as expected. 

However, as you can see in the previously referenced AN4075, the number of effective noise free bits at 800Hz and ±2 g is ~9. If you need to achieve higher resolution, I would recommend using the lowest possible ODR, High Resolution mode and set the LNOISE bit.

Best regards,

Tomas

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi,

Before looking into it, I want to double check one thing - by "least significant bit of X axis and Y axis" you mean Bit 0 or Bit 2 of OUT_X_LSB/OUT_Y_LSB registers? As shown in the datasheet and below, two LSBs of these registers are supposed to be "0" and do not care when calculating the 14-bit acceleration data.

pastedImage_1.png

pastedImage_2.png

Also keep in mind that the number of effective bits actually varies depending on the selected ODR and operating modes ((S)MODS[1:0] and LNOISE bits) as shown on page 7 of the AN4075.

Best regards,

Tomas 

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xiao_dong_yu
Contributor I

Hi Tomas Vaverka,

Thanks for your reply,

The LSB means the bit 2 of the register 0x02 or 0x04 (XD0 and YD0). 

Each time the read from these registers, the least four bits are either 0x8 or 0x0. I sampled lots of data, and got the same result.

I am wondering if my configuration is wrong.

The only register I set before sampling is by setting the 0x2A to 0x05, other registers are not configured and kept its default value.

Before reading register from 0x01 to 0x04, the status register 0x00 bit 1 and bit 0 are checked and they are '1'.

This picture is my I2C result of one read:

pastedImage_1.png

I tried to set the register 0x2B to 0x12 today, but got the same result.

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Xiaodong,

I have just performed some tests with MMA8451Q on the FRDM-KL25Z board and also found that Bit 2 of OUT_X_LSB/OUT_Y_LSB/OUT_Z_LSB registers remains zero at the ODR of 800Hz. At lower ODRs it changes as expected. 

However, as you can see in the previously referenced AN4075, the number of effective noise free bits at 800Hz and ±2 g is ~9. If you need to achieve higher resolution, I would recommend using the lowest possible ODR, High Resolution mode and set the LNOISE bit.

Best regards,

Tomas

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