I am using the FIFO on both the FXOS and FXAS and I have set both F_SETUP registers to be 0x5E (30 samples and continues mode) but when I read the data the last 7 samples are always zero. It appears if I go past 23 samples that is when the issue arises. Any explanation, verification or work around on this would be appreciated.
It is hard to say where the problem is, it might be a timing issue or something like that, so if you have a logic analyzer, can you please share here the collected data to know what is going on on the I2C bus, interrupt pins and other communication pins?
Attached you can find my example code reproducing your settings (FIFO in circular mode, watermark set to 30 samples, ODR set to 50 Hz) and running flawlessly. One thing to note is that the FXAS21002C requires that the WRAPTOONE bit is set for auto incrementing to address 0x01 (OUT_X_MSB register).