FXLS8967AF - Confused by "Auto-increment Address"

[andrewneil]

I'm not getting what the 'Auto-Increment Address' column in the FXLS8967AF datasheet  is trying to say:

Why is the 'Auto-increment Address' different from the 'Register Address' ?

What does it mean when a register has multiple 'Auto-increment' addresses listed?
eg, 02h/04h/06h/08h/0Ch/0Eh/10h for TEMP_OUT in all cases, and 04h/06h/08h/0Ch/0Eh/10h for VECM_LSB in Fast-read mode (F_READ=1).

[andrewneil]

But not if we look at the start of Table 20:

Why do INT_STATUS and TEMP_OUT have only one set of 'Auto-increment Address' sequences each?

Surely, those sequences should be different according whether F_READ=0 or 1; ie, according to whether the VECM and OUT_X/Y/Z MSBs are going to be skipped?

[diazmarin09]

Hello andrewneil,

I am pleased to contact you again. My apologies for the delayed response.

I know that the table seems confusing. Based on your feedback, I have already shared comments with the corresponding team.

I do recommend following the first byte from the first auto-increment address table and so on. In that way, the sequence will be affected by the F_READ bit.

I hope this information helps.

Regards,

David

[andrewneil]

A little progress here: 

https://community.nxp.com/t5/Sensors/FXLS8967AF-read-FIFO/m-p/1812752/highlight/true#M7959

The presentation in Table 20 is poor:

What is it supposed to mean with there being only one 'Auto-increment Address' (0Fh) for F_READ=0,
but three 'Auto-increment Addresses' (10h/0Ch/0Eh) for F_READ=1 ??

Having established that "Auto-increment Address" is actually supposed to mean "Next-Address after the Auto-increment", surely both columns should have just one address - like this:

And now it becomes clear that the Auto-increment sequences "loops-back" from BUF_Z_MSB (or BUF_Z_LSB when F_READ=1) to BUF_X_LSB.

So a Normal (F_READ=0) burst read of 13 bytes starting at 0x0B would get:

1. BUF_STATUS (0Bh)
2. BUF_X_LSB  (0Ch)
3. BUF_X_MSB  (0Dh)
4. BUF_Y_LSB  (0Eh)
5. BUF_Y_MSB  (0Fh)
6. BUF_Z_LSB  (10h)
7. BUF_Z_MSB  (11h)
8. BUF_X_LSB  (0Ch)
9. BUF_X_MSB  (0Dh)
10. BUF_Y_LSB  (0Eh)
11. BUF_Y_MSB  (0Fh)
12. BUF_Z_LSB  (10h)
13. BUF_Z_MSB  (11h)

[andrewneil]

@diazmarin09 - your comments would be appreciated...

Back to the question on the start of table 20:

at the start of Table 20:

Why do INT_STATUS and TEMP_OUT have only one set of 'Auto-increment Address' sequences each?

Surely, those sequences should be different according whether F_READ=0 or 1; ie, according to whether the VECM and OUT_X/Y/Z MSBs are going to be skipped or not?

I think what it should say is this:

yes?

[andrewneil]

@diazmarin09 

Sorry, the forum seems to put  posts in a weird order - so I'm having trouble following the sequence!

1. The F_READ bit is related to the Fast-read mode selection. I mean, if enabled, the output data format is limited to the most significant byte of the 12-bit sample.

The auto-increment address pointer automatically skips over the higher address for each axis' sample when performing a burst read operation of the current output data.

I get that.

But the table entry for TEMP_OUT (among others) shows that the auto-increment sequence is the same irrespective of whether F_READ is 0 or 1.

Surely, that's not right?

---

2. Note that such mechanism is related to your own reading or writing procedures.

I don't get what you're saying here.

You originally said:

If you start writing/reading a register with the auto increment mechanism enabled

but I don't see that there's any way to enable or disable the auto-increment mechanism - it just happens whenever you do a burst access?

So what did you mean by "enabling" it?

---

3. It does not make sense.

Is that referring to:

A follow-up question for the TEMP_OUT register:

"When SENS_CONFIG2[AINC_TEMP] = 0 the autoincrement mechanism skips this register."

With that setting enabled, what would happen if I were to start a burst read at address 01h - would TEMP_OUT be included or not? 

[diazmarin09]

Hello andrewneil,

I hope all is great with you. Thank you for using the NXP communities.

FXLS8967AF auto-increments the register write or read address so that every eighth clock edge latches the address for the next register write address. When the desired number of bytes has been written, a rising edge on the SPI_CS_B pin terminates the transaction.

For example, if you enable such feature, once you address and write the INT_STATUS register (0x00), the next byte sent will be written to the TEMP_OUT (0x01) register automatically and so on. And therefore, you can configure the device with a single data frame.

I hope this information helps.

Regards,

David

[andrewneil]

Yes, I get the basic idea of what auto-increment does - that wasn't the question.

The question was what those columns in Table 20 of the datasheet are trying to say:

1. Why is the 'Auto-increment Address' different from the 'Register Address' ?

2. What does it mean when a register has multiple 'Auto-increment' addresses listed?

In addition, there are references in the datasheet to "The auto-increment address range" - as if this is somehow different from the "normal" address range? What does this mean?

(btw, I'm using I2C rather than SPI)

[diazmarin09]

Hello andrewneil,

Please review the information below:

1. That column refers to the sequence that the auto-increment mechanism will follow once you address the normal register address.

2. If you start writing/reading a register with the auto increment mechanism enabled, such addresses refer to the “sequence” that the mechanism will follow. As you may noticed, the mechanism skips over the MSB registers.

For example, if you write the TEMP_OUT register with the auto-increment enabled, then the following registers will be affected. As mentioned, the mechanism skips over the MSB registers.

I hope that information helps.

Regards,

David 

[andrewneil]

OK, looking again at this:

For example, if you write the TEMP_OUT register with the auto-increment enabled, then the following registers will be affected. As mentioned, the mechanism skips over the MSB registers.

But that's not true - the mechanism should only skip the MSB addresses when F_READ=1.

When F_READ=0, a burst read starting at 01h (TEMP_OUT) does include all the LSB registers.

[diazmarin09]

Hello andrewneil,

1. The F_READ bit is related to the Fast-read mode selection. I mean, if enabled, the output data format is limited to the most significant byte of the 12-bit sample.

The auto-increment address pointer automatically skips over the higher address for each axis' sample when performing a burst read operation of the current output data.

2. Note that such mechanism is related to your own reading or writing procedures. I mean, you can perform single reading/writing operations.

3. It does not make sense. In that case, I do recommend starting your busts reading at address 0x02.

I hope this information helps.

Regards,

David   

[andrewneil]

2. If you start writing/reading a register with the auto increment mechanism enabled

Is it possible to enable/disable the auto increment mechanism?

[andrewneil]

Right - so those columns would be better headed as 'Auto-increment next Address(es)', then?

A follow-up question for the TEMP_OUT register:

"When SENS_CONFIG2[AINC_TEMP] = 0 the autoincrement mechanism skips this register."

With that setting enabled, what would happen if I were to start a burst read at address 01h - would TEMP_OUT be included or not?