SCST operation fault

[stanley_wu]

Hello, to meet ASIL B requirements, we used MPU partition and implemented SCST in 5 ms timer interrupt based on S32K144 MCU. But the problem is if an external interrupt was generated during SCST operation period, the system can't jump to the correct external interrupt service routine, and will always repeated in m4_scst_pass_control_to_user_interrupt routine. But if we disable MPU and run SCST in main loop (not in ISR), this failure will not happen.

As MPU is must to be used, we'd like to know why this failure happened? And is there any configuration incorrect in our system?

We are looking forward for your feedback urgently!

Thanks in advance!

[naveenm]

Hi,

The Cortex SCST Library uses it’s own interrupt vector table for dedicated tests only (Test ID 0-15). In case of these tests are interrupted by an ISR coming from the User Application the SCST Library is able to detect this “alien” interrupt and to forward it back into the User Interrupt Vector table. In such case the SCST API returns the M4_SCST_TEST_WAS_INTERRUPTED return value. Note, that this forwarding mechanism introduces some ISR latency which is documented in the SCST UM.

Second group of tests (ID 16-18) does not replace the interrupt vector table, but it disables all interrupts for some limited time, the ISR latency is also documented in the SCST UM.

Third group of test (ID 19-43) does not replace the interrupt vector table and does not disable interrupts. Documented latency is 0 for these tests.

The problem which I could observe is you execute some tests in ISR (Handler mode)?, see below

But if we disable MPU and run SCST in main loop (not in ISR), this failure will not happen….

Note, that invocation of some tests is not allowed in the Handler mode, as it is documented in the SCST UM, please refer to Table 10 Core Test Invocation Mode.

Hope it helps.

Regards,

NaveenM

[stanley_wu]

Hi NaveenM, thanks for your reply! It's really help us.  As we want to use partition for ASIL B app and QM app, and we don't use an OS, we can only run the ASIL app in ISR, and QM app runs in thread unprivileged. That's why the failure happened.

Here we have a further question: how can we runs ASIL app in thread privileged without an OS? We don't know how to shift the system between thread privileged and thread unprivileged.

[naveenm · Accepted solution]

Hi,

Switching between both Thread Privileged/Unprivileged can be done inside the SVCall,  where SVCall is an exception that is triggered by the SVC instruction.

Inside the SVCall handler user can switch between Privileged/Unprivileged modes by writing the nPRIV bit in  the CONTROL register, see below.

More details can be found in the Cortex™-M4 Devices Generic User Guide, which can be downloaded from ARM pages.

Here is example of the assembly code.

  /* Set nPRIV bit*/

   MRS     R2,CONTROL     /*Read CONTROL */

   ORR     R2,R2,#1          /*Set nPRIV  */

   MSR     CONTROL,R2  /* Write Control */

   /* Clear nPRIV bit */              

    MRS     R2,CONTROL   /* Read CONTROL */

    BIC       R2,R2,#1          /* Clear nPRIV bit  */

    MSR     CONTROL,R2  /* Write CONTROL */

Hope this helps.

Regards,

NaveenM