S32K344 MPU allocate

[liyongfeng]

How is data from different ASIL levels partitioned in S32K344? To implement low-level code, high-level data cannot be accessed.   Doesn`t partitioning involve flash?

Region	Description	Privileged Access	Unprivileged Access
0	Whole memory map	No Access	No Access
1	ITCM	Read/Write	No Access
2	Program Flash	Read-Only	Read-Only
3	Data Flash	Read-Only	Read-Only
4	DTCM	Read/Write	No Access
5	SRAM + STACK	Read/Write	Read/Write
5	ASIL A	Read/Write	No Access还是Read-Only?
5	ASIL B	Read/Write	No Access还是Read-Only?
5	ASIL C	Read/Write	No Access还是Read-Only?
6	SRAM NC	Read/Write	Read/Write
7	SRAM SHARED	Read/Write	Read/Write
8	AIPS_0	Read/Write	Read/Write
9	AIPS_1	Read/Write	Read/Write
10	AIPS_2	Read/Write	Read/Write
11	QSPI Rx	Read/Write	Read/Write
12	QSPI AHB	Read/Write	Read/Write
13	PPB	Read/Write	Read/Write

[Yashwant_Singh]

Hi Liyongfeng,

Please refer to XRDC chapter of RM to see how one can partition different modules and memories into different domains that have different access levels to enable functions with different ASILs on the same chip.

Thanks!

-Yashwant