Problem Description According to our hardware design, only use DDR0, does not use DDR1. Current BSP and SDK of S32V is based on two DDRs, so we would like to consult how to modify and the guidance advice.
Because this change affects the memory layout, so we think SDK and BSP may need to make the appropriate changes. In particular SDK, we are not familiar with its implementation. Could NXP please teach us how to modify and some guidance advice.
Here are some of the possible changes that we have listed (If there are omissions, please point out)