S32V: SRC_GPR Registers: Write failures?

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S32V: SRC_GPR Registers: Write failures?

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ektasachdev
Contributor II

Hi,

 

I'm trying to configure the PCIE related registers on the S32v EVB board and I keep encountering strange behaviour.

For example, once QNX is up and running on the S32V EVB board, I tried reading the SRC_GPR5 register (address: 0x4007C110). The read succeeded and I got the following value -- 0x12500208 .

 

However, if I try to write to this register after the OS has booted, I get a bus error.

 

I can easily configure this registers in IPL and u-boot. I can't seem to do it after QNX is up and running. I've checked that the register itself is R/W and is a non-secure register (based on the TRM).

 

Can someone let me know if the TRM was updated or there is anything special I need to do to write to these registers once the OS is up and running?

 

 


Thanks,

Ekta

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kushalshah13
NXP Employee
NXP Employee

Hi Ekta,

From your question, it seems that it is some prevention mechanism in QNX OS that is preventing access to this register.

I will recommend to contact QNX for support.

Regards,

Kushal

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