S32M244 halt CPU problem

[waldluis]

Hello,

I am trying to find a way to stop the core of the S32M244 on the S32M24xEVB-L064 evaluation board. I am connected to the board via PJTAG. The plan is to perform a memory mass erase, stop the core, load a RAM bootloader, then start the core to execute the RAM bootloader. The procedure is done as follows:

1. Drive reset low 

2. Perform a mass erase with MDM_AP

3. Stop the CPU

    1. Set MDM_CONTROL debug request

    2. Release reset

    3. Stop CPU with DHCSR

    4. Drive reset high

    5. Check if CPU is stopped

    6. Clear the MDM_CONTROL register

4. Drive reset high

5. Load bootloader code into RAM

6. Start bootloader

This procedure works in about 60% of the time. Sometimes an error occurs when checking if the CPU is stopped. After that it seems like the connection is broken, because the register readouts all return the same value, which appears to be buffered in the DAP.

Setting the MDM_CONTROL debug request should force the CPU to stop, which doesn't happen. The core can only be stopped by setting the bits in the DHCSR directly.

Has anyone experienced this problem or knows of a straightforward procedure to stop the core without any errors?

[danielmartynek · Accepted solution]

Hello @waldluis,

You mentioned these steps:

2. Release reset

4. Drive reset high

4. Drive reset high for the second time.

But the reset is an open-drain pin, it should not be driven high externally.

I tested it with this j-link script, and everything works correctly.

// Step 1: Connect
device S32M244
si SWD
speed 4000
connect
sleep 100

// Step 2: Reset
R0
sleep 100

// Step 3: Read MDM_AP
swdwritedp 2, 0x01000000
sleep 100

// Step 4: MDM_AP Status
swdreadap 0  
swdreadap 0
sleep 100

// Step 5: MDM_AP Control
swdreadap 1  
swdreadap 1
sleep 100

// Step 6: Write MDM-AP CONTROL[2] Set to force the core to halt
swdwriteap 1,0x4
sleep 100

// Step 7: Release reset
r1
sleep 1000

// Step 8: MDM_AP Status
swdreadap 0  
swdreadap 0
sleep 100

The core is always halted after the reset is released:

BR, Daniel

[waldluis]

Hello @danielmartynek

Thank you for your quick and helpful response.
I could reproduce your script with the J-Link on my eval-board.
The main difference was the communication speed. I had it set to 1 MHz, which works fine except when stopping the CPU. After changing this for the stop process, this works every time. Is the communication speed specified in any datasheets? It seems to be a crucial factor in the process. The J-Link also fails sometimes at 1 MHz.
With the proprietary device I use, the debug request with the MDM_AP has no effect. The only way to stop the CPU is by modifying the DHCSR directly. I can't explain why, but that's fine as it now works every time.

[danielmartynek]

Hi @waldluis,

Yes, SWD and JTAG are specified in the DS, it support higher speeds than 1MHz.

Table 76. SWD electrical specifications

Table 77. JTAG electrical specifications

https://www.nxp.com/docs/en/data-sheet/S32M2xx_DS.pdf

Can you use longer wait loops after the swdwrite to the control register and especially after the reset_b release?

Regards,

Daniel

[waldluis]

Hello @danielmartynek

Thank you,
I did some testing with different timeouts after the register write and reset release, but it didn't make much of a difference. Changing to a higher frequency was the big factor, as it made a reliable stop sequence possible.