hi,team.while i reading the dithering part of S32K-rm, the figure47-120:channel(n) is in EPWM Mode with PWM Edge Dithering, i found it add one clock to pwm period? is it wrong?shouldn't it keep the same?
the description above the figure explains the duty cycle add one clock when the accumulator overflows but not the pwm period. I think the pwm period add one clock when it is period dithering.