why the pwm period add one clock in edge-dithering?

[chip_designer]

hi,team.while i reading the dithering part of S32K-rm, the figure47-120:channel(n) is in EPWM Mode with PWM Edge Dithering, i found it add one clock to pwm period? is it wrong?shouldn't it keep the same?

[danielmartynek]

Hi @chip_designer,

This happens when the accumulator overflows.

It is explained in the description above the figure you are referring to.

BR, Daniel

[chip_designer]

the description above the figure explains the duty cycle add one clock when the accumulator overflows but not the pwm period. I think the pwm period add one clock when it is period dithering.

[danielmartynek]

Hi,

You are right, the period should not be changed with PWM Edge Dithering.

Let me report that, thank you for pointing it out.

Best regards,

Daniel