why the pwm period add one clock in edge-dithering?

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why the pwm period add one clock in edge-dithering?

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chip_designer
Contributor I
hi,team.while i reading the dithering part of S32K-rm, the figure47-120:channel(n) is in EPWM Mode with PWM Edge Dithering, i found it add one clock to pwm period? is it wrong?shouldn't it keep the same?
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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @chip_designer,

This happens when the accumulator overflows.

It is explained in the description above the figure you are referring to.

 

BR, Daniel

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chip_designer
Contributor I

the description above the figure explains the duty cycle add one clock when the accumulator overflows but not the pwm period. I think the pwm period add one clock when it is period dithering.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

You are right, the period should not be changed with PWM Edge Dithering.

Let me report that, thank you for pointing it out.

 

Best regards,

Daniel

 

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