why SRAM segmented to two banks?

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why SRAM segmented to two banks?

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Contributor II
hello, I select S32K14x as MCU for my project. when I read datasheet and user manual, noticed that there is two bank (32KB as SRAM_L and 28KB as SRAM_U) in chip. they are separated from each other in bus access way.  1. my question is about advantages of this method in MCU? (why there is two SRAM block?) 2. accessing time is different for them? 3. when we should use each of two banks?  Thanks.
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Contributor II

Thanks for reply.

what is the mean of Core System Bus? which part of MCU is in this section?

can use both Core Code and Core System bus simultaneously?  (what is application in this mode?)

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NXP TechSupport
NXP TechSupport

It is related to XBAR ports.

davidtosenovjan_0-1600952248248.png

Over code bus port instruction are being fetched to be executed, core system bus is actually data bus.

 

 

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NXP TechSupport
NXP TechSupport

It offers certain advantage for performance optimization.

SRAM_L offers single-cycle access for core code bus whilst SRAM_U offers single-cycle access for core system bus. Other accesses are backdoor and these take two clocks.

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