the classification of SRAM

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the classification of SRAM

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yin_qiu
Contributor III

dear NXP experts:

in the S32K312 project, in the ld file ,we can find there is 32K int_sram 、32K int_sram_no_cacheable and 32K int_sram_shareable, could you  pls  tell me the detail distinguish about this classification?

thans a lot.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

int_sram - no constraints
int_sram_no_cacheable - expected to be non-cacheable (interrupt vectors and other reasons)
int_sram_shareable - expected to be shared with multicore

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davidtosenovjan
NXP TechSupport
NXP TechSupport

int_sram - no constraints
int_sram_no_cacheable - expected to be non-cacheable (interrupt vectors and other reasons)
int_sram_shareable - expected to be shared with multicore

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WenWenDar
Contributor II

Hi, @davidtosenovjan 

After modifying the sizes of int_stram, int_stram_no-ucacheable, and int_stram_sthareable in the linker file, there is a  Data access violation (CFSR. DACCVIOL, MMFAR), At data address 0x20408594.

The chip is S32K312, and the linker file is as follows

linker_flash_s32k312_icf.JPG

Could you give me some advice? thank you!

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yin_qiu
Contributor III

thank you pretty much and are you familiar with ITCM and DTCM?

can I take use of them as normal ram?

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davidtosenovjan
NXP TechSupport
NXP TechSupport

ITCM/DTCM are fast local two port memories intended either for fast instruction or fast data access.

Front-door accesses to TCM memories are as fast as access to cache, back-door accesses are slower.

Also these port are mapped to different address ranges - Front-door address range for related core accesses and back-door address range for any core or other master, over this port TCM memories may act as system memories.

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