the PWM output frequency issue on S32K3

[zp001]

Hello,

There is a problem about PWM output frequency, the configuration of PWM is as below:

eMIOS_Mcl configuration:

1. eMIOS_0 source clock is 160Mhz
2. eMIOS_0 clock divider is 200 and the default period is 65535

PWM channel configuration:

1. clock prescaler is DIV_1
2. prescaler clock source is EMIOS_PWM_SRC_PRESCALED_CLOCK
3. the period is 65534

the frequency of this channel should be calculated by below formula:

output frequency = 160000000 / 200 / 65534 = 12.2Hz

but I got a 3.67hz waveform.

It looks like the source clock divided by 3 once again.

I have double checked the configurations and can't find any clue.

I'd like to know why this phenomenon should occur.

RTD is 2.0.1 

S32DS V3.5

Thanks!

[PetrS · Accepted solution]

Hi,

your calculation is correct, but in your project the core clock is running from FIRC, not the PLL. This makes that difference. 
For clock init use below function

/* Initialize clock */
Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);

BR, Petr

[zp001]

Hello,

I tried to read PLL clock via Clock_Ip_GetFreq(PLL_CLK);

The PLL clock is zero, that is inconsistent with the clock map.