s32k344 CMU_FC questions

[FabioG]

Hi there,

I have some questions about CMU_FC and related s32k344 reference manual's chapter 56.

1) In 56.3.3 Clocking tab Table 310  p. 2194 RM, it is mentioned "bus_clock" witth the description: "Clock signal on which register read/write operation is performed" . 

No other indication is done in this chapter. so is this bus_clock the AIPS_SLOW_CLK as indicated in chapter 24, par. 24.6.1.7 pp915, Tab.132? if not which clock is it ?? I must know it in order to set RCCR[REF_CNT] register.

2) 56.5.2 "Programming HFREF and LFREF" at step 2 of the example, is said
"Determine the specified variation of the monitored_clock (1.1%)."

and at point 5:
"Determine the specified variation of the reference_clock (3.3%)."

So is necessary the variation of monitored clocks and reference clocks of the following clocks according to figure "Figure 115",  chapter 24.8 "Clock monitoring", pp 960:

a)AIPS_PLAT_CLK

b)FIRC_CLK

c)CORE_CLK

d)FXOSC_CLK

Where I can find the real values for S32K344EHT1MPBST?

In datasheet in chapter 11, 11.1 FIRC is mentioned the magnitude FACC=-5% to 5% is this the value I need for FIRC in HFREF, LFREF computation?

for FXOSC in datasheet (11.4 FXOSC) there is no hypothetical magnitudes, I was thinking about the precision of crystal oscillation, bit it is much smaller of the magnitudes mentioned  in the examples of the calculation of hfref,lfref ...

and what about other clocks....

So where I find data about  AIPS_PLAT_CLK, FIRC_CLK, CORE_CLK, FXOSC_CLK ?

Best regards.

Fabio G

[danielmartynek · Accepted solution]

Hi @FabioG,

1.

Yes, it is the Register Interface clock

2.

The accuracy of SIRC and FIRC is specified in the DS, as you mentioned.

The tolarenace of the external oscillators (FXOSC and SXOSC) depends on the toreance of the crystal/external resonator.

For PLL, there is a specification of its Jitter.

AIPS_PLAT_CLK and CORE_CLK can be derived either from FIRC or PLL, therefore, their accuracy is given by the accuracy of FIRC or PLL.

RM, Section 24.3.10 S32K344, S32K324, S32K314, S32K322, S32K341 and S32K342 clock system diagram.

BR, Daniel