I used S32K 148. When I collected ADC, there was a great chance that there would be a big error.When I look at the data sheet, I find the following passage is not very clear.Can you explain it to me in detail?
NOTE
single ADC. For parallel/simultaneous operation of both
ADCs, either for sampling the same channel by both ADCs
or for sampling different channels by each ADC, some
amount of decrease in performance can be expected. Care
must be taken to stagger the two ADC conversions, in
particular the sample phase, to minimize the impact of
simultaneous conversions.
Hi, it means simultaneous operation of both ADC may induce unspecified decreasing of performance (caused by crosstalk) what’s however may not be issue for certain applications.
For accurate conversion only one ADC needs to be active in the sampling phase.