Hi,
The S32K144 MCU supports both.
There are 16 priority levels configurable in the 4 most significant bits in IRQn fields in NVIC IPRn registers. See Chapter 7.2.1. RM. The lower the priority number is set, the higher priority. So priority 0 is the highest priority level. And all interrupts are set to this level out of reset.
Note: The S32_NVIC_IP_PRIn(x) function from the S32K144.h header file (S32DS) doesn’t shift the number to the 4 most significant bits of IRQn. Therefore, to set priority number 4, for instance, it is necessary to put it like this:
S32_NVIC->IP[x] |= S32_NVIC_IP_PRIn(0x40); // priority number 4
Preemption:
An interrupt with a higher priority level preempts an interrupt with lower priority level. For example, an interrupt with priority number 2 preempts interrupt with priority number 3 and higher.
If multiple pending interrupts have the same priority, the pending interrupt with the lowest exception number is executed first.
Subpriority:
Priority grouping is configurable in the AIRCR[PRIGROUP] register.
And it is well explained in ARM Cortex M4 Generic User Guide, Chapter 4.3.5.
A number written to the PRIGROUP basically divides the IPRn[IRQn] to bits that configure the preemption and subpriorities. Since the S32K144 implements only 16 priority levels, configurable in the 4 most significant bits of IRQn, the PRIGROUP must be set to number that is greater or equal to 4.
Then, if PRIGROUP = 4, the IRQn[7-5] bits configure all preemptive interrupt levels and the IRQn[4] bit configures subpriority levels.
Note: By default, the AIRCR register is a read-only register. In order to set the PRIGROUP field, it is necessary to write to VECTKEYSTAT the number 0x5FA along with the PRIGROUP number, otherwise the processor ignores the write.
S32_SCB->AIRCR = 0x5FA0400;
[31-16] VECTKEYSTAT = 0x5FA
[10-8] PRIGROUP = 0x4
Regards,
Daniel
