Hi @zjldabing
yes, it's caused by data cache. Let me copy here from some other discussion:
The default project setting enabled Cache, and the lwip heap memory was allocated from cacheable region. Thus there are risks about data inconsistency when CPU and EMAC uDMA access asynchronously. Two way to avoid this issue:
① Just disable the D-cache, the original Lwip_s32k344 demo use the same way. It's convenient, but lower running efficiency for other applications.
② Allocate the lwip heap from non-cacheable region. Thus the cache can keep enable, it's good. When use this way, you need to make below changes:
a) Increase the non-cacheable region (decrease shareable region) in linker file and add the lwip non-cacheable heap region for next use.


b) Add lwip memory allocation macro in .mex tcpip component "user setting" page, thus it would be generated in lwipcfg.h, and to replace the default allocation way in "arch.h" which allocate memory from shareable region.

Regards,
Lukas