about S32K14X VLPS abort Reason

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about S32K14X VLPS abort Reason

989 Views
shijie_zheng
Contributor III

Hi:

according to [S32K1xx Series Reference Manual.pdf], Register SMC_PMCTRL bit3:VLPSA will be set to 1 when stop/vlps mode entry was aborted,

Is there a register or a way that can see the reason of the stop/vlps mode entry abort?

 

 

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3 Replies

972 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

The reason is always an interrupt.

Please take a look at the RM, section 40.4.2.3 Aborted very low power stop mode entry.

I think you can read the VLPSA flag in the interrupt handlers to determine which interrupt aborted it.

 

BR, Daniel

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966 Views
shijie_zheng
Contributor III

Hi danielmartynek:

thank you for your reply.

Does these interrupt handler  refer to the handlers which I configured in "startup_S32K148.S"?

So, I need to read VLPSA flag in all of these Handers, If someone interrupt is triggered and the VLPSA flag is 1(the previous stop mode entry was aborted), VLPS mode entry is aborted by this interrupt,

is my understanding correct?

/* startup_S32K148.S Exception Handlers as follows*/
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA4_IRQHandler
def_irq_handler DMA5_IRQHandler
def_irq_handler DMA6_IRQHandler
def_irq_handler DMA7_IRQHandler
def_irq_handler DMA8_IRQHandler
def_irq_handler DMA9_IRQHandler
def_irq_handler DMA10_IRQHandler
def_irq_handler DMA11_IRQHandler
def_irq_handler DMA12_IRQHandler
def_irq_handler DMA13_IRQHandler
def_irq_handler DMA14_IRQHandler
def_irq_handler DMA15_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler MCM_IRQHandler
def_irq_handler FTFC_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler FTFC_Fault_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler RCM_IRQHandler
def_irq_handler LPI2C0_Master_IRQHandler
def_irq_handler LPI2C0_Slave_IRQHandler
def_irq_handler LPSPI0_IRQHandler
def_irq_handler LPSPI1_IRQHandler
def_irq_handler LPSPI2_IRQHandler
def_irq_handler LPI2C1_Master_IRQHandler
def_irq_handler LPI2C1_Slave_IRQHandler
def_irq_handler LPUART0_RxTx_IRQHandler
def_irq_handler Reserved48_IRQHandler
def_irq_handler LPUART1_RxTx_IRQHandler
def_irq_handler Reserved50_IRQHandler
def_irq_handler LPUART2_RxTx_IRQHandler
def_irq_handler Reserved52_IRQHandler
def_irq_handler Reserved53_IRQHandler
def_irq_handler Reserved54_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler Reserved58_IRQHandler
def_irq_handler Reserved59_IRQHandler
def_irq_handler ERM_single_fault_IRQHandler
def_irq_handler ERM_double_fault_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler LPIT0_Ch0_IRQHandler
def_irq_handler LPIT0_Ch1_IRQHandler
def_irq_handler LPIT0_Ch2_IRQHandler
def_irq_handler LPIT0_Ch3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler Reserved69_IRQHandler
def_irq_handler Reserved70_IRQHandler
def_irq_handler SAI1_Tx_IRQHandler
def_irq_handler SAI1_Rx_IRQHandler
def_irq_handler SCG_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler QSPI_IRQHandler
def_irq_handler Reserved82_IRQHandler
def_irq_handler Reserved83_IRQHandler
def_irq_handler PDB1_IRQHandler
def_irq_handler FLEXIO_IRQHandler
def_irq_handler SAI0_Tx_IRQHandler
def_irq_handler SAI0_Rx_IRQHandler
def_irq_handler ENET_TIMER_IRQHandler
def_irq_handler ENET_TX_IRQHandler
def_irq_handler ENET_RX_IRQHandler
def_irq_handler ENET_ERR_IRQHandler
def_irq_handler ENET_STOP_IRQHandler
def_irq_handler ENET_WAKE_IRQHandler
def_irq_handler CAN0_ORed_IRQHandler
def_irq_handler CAN0_Error_IRQHandler
def_irq_handler CAN0_Wake_Up_IRQHandler
def_irq_handler CAN0_ORed_0_15_MB_IRQHandler
def_irq_handler CAN0_ORed_16_31_MB_IRQHandler
def_irq_handler Reserved99_IRQHandler
def_irq_handler Reserved100_IRQHandler
def_irq_handler CAN1_ORed_IRQHandler
def_irq_handler CAN1_Error_IRQHandler
def_irq_handler Reserved103_IRQHandler
def_irq_handler CAN1_ORed_0_15_MB_IRQHandler
def_irq_handler CAN1_ORed_16_31_MB_IRQHandler
def_irq_handler Reserved106_IRQHandler
def_irq_handler Reserved107_IRQHandler
def_irq_handler CAN2_ORed_IRQHandler
def_irq_handler CAN2_Error_IRQHandler
def_irq_handler Reserved110_IRQHandler
def_irq_handler CAN2_ORed_0_15_MB_IRQHandler
def_irq_handler CAN2_ORed_16_31_MB_IRQHandler
def_irq_handler Reserved113_IRQHandler
def_irq_handler Reserved114_IRQHandler
def_irq_handler FTM0_Ch0_Ch1_IRQHandler
def_irq_handler FTM0_Ch2_Ch3_IRQHandler
def_irq_handler FTM0_Ch4_Ch5_IRQHandler
def_irq_handler FTM0_Ch6_Ch7_IRQHandler
def_irq_handler FTM0_Fault_IRQHandler
def_irq_handler FTM0_Ovf_Reload_IRQHandler
def_irq_handler FTM1_Ch0_Ch1_IRQHandler
def_irq_handler FTM1_Ch2_Ch3_IRQHandler
def_irq_handler FTM1_Ch4_Ch5_IRQHandler
def_irq_handler FTM1_Ch6_Ch7_IRQHandler
def_irq_handler FTM1_Fault_IRQHandler
def_irq_handler FTM1_Ovf_Reload_IRQHandler
def_irq_handler FTM2_Ch0_Ch1_IRQHandler
def_irq_handler FTM2_Ch2_Ch3_IRQHandler
def_irq_handler FTM2_Ch4_Ch5_IRQHandler
def_irq_handler FTM2_Ch6_Ch7_IRQHandler
def_irq_handler FTM2_Fault_IRQHandler
def_irq_handler FTM2_Ovf_Reload_IRQHandler
def_irq_handler FTM3_Ch0_Ch1_IRQHandler
def_irq_handler FTM3_Ch2_Ch3_IRQHandler
def_irq_handler FTM3_Ch4_Ch5_IRQHandler
def_irq_handler FTM3_Ch6_Ch7_IRQHandler
def_irq_handler FTM3_Fault_IRQHandler
def_irq_handler FTM3_Ovf_Reload_IRQHandler
def_irq_handler FTM4_Ch0_Ch1_IRQHandler
def_irq_handler FTM4_Ch2_Ch3_IRQHandler
def_irq_handler FTM4_Ch4_Ch5_IRQHandler
def_irq_handler FTM4_Ch6_Ch7_IRQHandler
def_irq_handler FTM4_Fault_IRQHandler
def_irq_handler FTM4_Ovf_Reload_IRQHandler
def_irq_handler FTM5_Ch0_Ch1_IRQHandler
def_irq_handler FTM5_Ch2_Ch3_IRQHandler
def_irq_handler FTM5_Ch4_Ch5_IRQHandler
def_irq_handler FTM5_Ch6_Ch7_IRQHandler
def_irq_handler FTM5_Fault_IRQHandler
def_irq_handler FTM5_Ovf_Reload_IRQHandler
def_irq_handler FTM6_Ch0_Ch1_IRQHandler
def_irq_handler FTM6_Ch2_Ch3_IRQHandler
def_irq_handler FTM6_Ch4_Ch5_IRQHandler
def_irq_handler FTM6_Ch6_Ch7_IRQHandler
def_irq_handler FTM6_Fault_IRQHandler
def_irq_handler FTM6_Ovf_Reload_IRQHandler
def_irq_handler FTM7_Ch0_Ch1_IRQHandler
def_irq_handler FTM7_Ch2_Ch3_IRQHandler
def_irq_handler FTM7_Ch4_Ch5_IRQHandler
def_irq_handler FTM7_Ch6_Ch7_IRQHandler
def_irq_handler FTM7_Fault_IRQHandler
def_irq_handler FTM7_Ovf_Reload_IRQHandler

 

 

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961 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

For debugging purposes, I think the source of VLPSA could be found this way.

But you would need to read the VLPSA flag in just the interrupt handlers that are enabled like wake-up sources at the time the MCU enters VLPSA.

It should be noted that the VLPSA flag can't be cleared in the handlers, it will stay set until the MCU is reset or the next VLPS transition is successful.

Also, this flag will not get set if STOP1/STOP2 get aborted.

 

Regards,

Daniel

 

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