XRDC in s32k344 running in lockstep mode

[FabioG]

HI There

in XRDC module in a s32k344 running in lockstep , I read in manual that  master core could be CM7 or AHBP or AXI. So i am convinced that a s32k344 in lockstep mode is to referring to a AHBP core master access, is it true?

in RTD4.0.0 in   Rm RTD module ,the  core types are the following:

typedef enum
{
XRDC_CORE_M7_0 = 0x00U,
XRDC_CORE_HSE = 0x03U,
XRDC_CORE_M7_1 = 0x04U
} Xrdc_Ip_MasterCoreType;

It seams that lockstep configuration is not suited for these RTD ...?

What is the situation about XRDC in lockstep mode for s32k344 ?

best regards,

Fabio

[VaneB · Accepted solution]

Hi @FabioG 

A small explanation of how Lockstep Core works is that two identical processors are initialized to the same state, and they receive the same inputs (code, bus operations, and asynchronous events), so during normal operation, the two processors operate in parallel, executing the same set of instructions simultaneously. The key feature of lockstep is that both cores execute the same instructions and compare their results at every step to ensure they match. If a discrepancy is detected, it indicates a potential error or fault in one of the cores, triggering a fault-handling mechanism.

Because of this behavior, in lockstep, there is only a reference to M7_0 and M7_1 would be N/A. 

B.R.

VaneB

[FabioG]

Hi There,

Referring Figure8 Block Diagram page 24 Reference manual:

It seems that CM7_1 accesses to bus via MDAC4, when XRDC is enabled. So in Lockstep mode i have to manage only MDAC0 (CM7_0)?

Regards

Fabio