Why is S32K144 in STOP1 mode, CLKOUT also has bus_clk output?

[PYGC]

The description of STOP1 will disable the system clock and bus clock

I output the bus clock through CLKOUT, and found that there is still clock output after entering STOP1.

[danielmartynek]

Hi @PYGC,

Can you disconnect the debugger and power cycle the MCU before it goes to the STOP1 mode?

Thank you,

BR, Daniel

[PYGC]

Yes, I am using S32K144EVB-Q100 Rev C1,

• 12V power supply
• disconnected J106 and J8 (cut wires)

CLKOUT still outputs BUS_CLK

[danielmartynek]

Hi @PYGC,

Do you disable FIRC, SOSC and SPLL in the RUN mode?

Is SIRC the system clock?

Can you measure the consumption of the MCU?

Thanks,

Daniel

[PYGC]

I use FIRC 48MHz as clock source, SOSC and SPLL is disabled.

I get power consumption from DC power supply, which may not be accurate.

RUN Mode:

STOP1 Mode:

STOP1 CLK_OUT:

And I tried to use SIRC as clock source before entering STOP1, close the FIRC, SOSC, SPLL

But CLK_OUT still has 4MHz output

(Fbus_clk = Fcore_clk = SIRC / 2 = 4MHz)

[danielmartynek]

Hi @PYGC,

I'm just testing it and I can reproduce what you see.

SYS_CLK is gated off while BUS_CLK is running in STOP1.

It is being investigated.

BR, Daniel

[danielmartynek]

Hello @PYGC,

I'm sorry for the delay.

The issue is still under an internal discussion / investigation unfortunately.

BR, Daniel

[danielmartynek · Accepted solution]

Hello @PYGC,

The BUS_CLK clock signal that goes to the CLKOUT external pin as selected with SIM_CHIPCTL[CLKOUT] is the main trunk for the bus clock. This BUS_CLK is not gated in STOP1. But the bus clock that are generated from the BUS_CLK are gated in STOP1 mode before being driven to the peripherals. Thus the RM is accurate, we just need to interpret the "bus clocks are all gated" as the clocks to the peripherals and not the BUS_CLK signal that is sent to the CLKOUT pad.

Regards,

Daniel