Hi,
the Accepance mask registers are used to filter incoming ID. There is bit2bit correspondence between received ID, mask and programmed MB ID (or RXFIFO ID filter elements). The mask says if corresponding incoming ID bit is compared with programmed ID bit.
If mask bit is cleared the incoming ID bit is not compared, it is don’t care. If mask bit is set, then there must be exact match between incoming ID bit and programmed ID bit. To receive a message into a MB/RXFIFO all relevant bits with mask bit set must be equal to programmed one.
There are following rules for message filtering for different FlexCAN module configuration (assume module with 32 MBs)
a) When MCR[FEN]=0, no RX FIFO
MCR[IRMQ]=0: MB0-MB31 use RXGMASK except MB14 uses RX14MASK and MB15 used RX15MASK
MCR[IRMQ]=1: MB0-MB31 use RXIMR0-RXIMR31
b) When MCR[FEN]=1, RX FIFO used
MCR[IRMQ]=0: all RX FIFO ID elements uses RXFGMASK, rest od MBs use RXGMASK except MB14 uses RX14MASK and MB15 used RX15MASK (only if MB14/15 are not occupied by RXFIFO ID table)
MCR[IRMQ]=1: RX FIFO ID elements uses RXIMRx and RXFGMASK depending the CTRL2[RFFN] setting
BR, Petr
