Hi @jingfang
There is no such range of System Oscillator (SOSC) clock monitor.
Regarding the question LOL and LOC, according to the RM:
LOC reset is enabled when SOSC clock monitor is enabled. Its error flag is set when SOSC pulses are not detected for 8 to 16 clock cycles of SIRC/256. Hence, the LOC indication through reset to the system from the time when oscillator is cut off will vary from 256 μs to 512 μs.
As well LOL reset is enabled when PLL clock monitor is enabled. Its error flag is set when PLL the PLL reference is out of range and is constantly modulated such that 3 consecutive un-locked samples of the reference clock are generated.
Also, refer the DS, Table 34. SPLL electrical specifications, D_UNL.
B.R.
VaneB
