What is S32K3 PLL Loss of Lock?

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What is S32K3 PLL Loss of Lock?

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li3
Contributor II

Hi NXP,

    I am looking at the PLL Loss of Lock in the S32K3 chip manual, please answer my questions below.

    1.What is PLL Loss of Lock?

   2.What do the formulas in the manual mean?

li3_0-1728209722708.png

Best regards,

Li 3.

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PavelL
NXP Employee
NXP Employee

Hi,

PLL LOL is permanently turned on. It is one of the Destructive reset sources (please refer to chapter 31.3.3 in RM_rev9).

Best regards,

Pavel

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1,441 Views
li3
Contributor II

Hi NXP,

1.According to the manual, LOL can only be used in PLL functional mode, so PLL is configured to automatically open LOL in functional mode.

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Best regards,

Li 3.

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1,500 Views
li3
Contributor II

Hi NXP,

PLL LOL Destructive reset Demoted to interrupt Can only write program configuration registers?

li3_0-1728369761799.png

Best regards,
Li 3.

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li3
Contributor II
Hello. Is that what I said?
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PavelL
NXP Employee
NXP Employee

Hello,

yes.

Best regards,

Pavel

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PavelL
NXP Employee
NXP Employee

Hi,

yes, set field DEST_RST9_AS_IPI to 1 (of register DCMRWP3) to configure a destructive reset to interrupt.

Best regards,

Pavel

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1,480 Views
li3
Contributor II

Hi NXP,

The DCMRWF2.PLL1_LOL_RST _EN bit is used to set the LOL destructive restart or interrupt. What is the relationship between this bit and the DCMRWP3.DEST_RST9_A S_IPI bit?

li3_0-1728377790268.png

Best regards,

Li 3.

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PavelL
NXP Employee
NXP Employee

Hi,

DCMRWF2 is related to the Functional reset (this is not available for all members of S32K3 family), DCMRWP3 is related to the destructive reset. Please refer to Chapter 31 and 33 in RM_rev9 for details about reset.

Best regards,

Pavel

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PavelL
NXP Employee
NXP Employee

Hi Li 3,

since PLL is a general, common used block, please refer to PLL general description Phase-locked loop - Wikipedia.

1. PLL Loss of lock means big failure of PLL - output frequency goes over acceptable limits.

2. The formulas show how is PLL's output frequency calculated during different modes.

Best regards,

Pavel

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li3
Contributor II
Hi NXP,
Think you for your reply.
1.How to configure PLL LOL in S32DS software?
2.How does LOL automatically monitor the PLL clock?

Best regards,
Li 3.
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1,514 Views
PavelL
NXP Employee
NXP Employee

Hi,

PLL LOL is not configurable. There is only configurable lock counter - please refer to RM_rev9 30.6.7 PLL Calibration Register 2 (PLLCAL2) for details.

LOL monitor is a part of PLL IP, so there are no more details to be shared.

As it is written in RM: PLL LOL is intended for detection of gross failures. Use CMUs for accurate frequency monitoring.

Best regards,

Pavel

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li3
Contributor II
Hi,
Think you for your reply.
How to enable PLL LOL?
Best regards,
Li 3.
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