Hi,
I am considering to use S32K1xx to implement a very responsive SPI slave which can response to within the same SPI command transaction.
Supposes that:
There is one perticular command needs quick response, better within the same transaction.
How to program the S32K1xx MCU to achieve this? Can LPSPI do the job?
Best regards and thanks in advance!
Solved! Go to Solution.
Hello @yfliu,
Yes, the match interrupt asserts after the first 8bit frame is received if the data match.
Regarding WORD / FRAME side, I think it is explained in the description of the FRAMESZ register.
The Frame Complete Flag (FCT) asserts when the frame is complete which can consists of many words.
Whereas the Word Complete Flag (WCF) asserts on completion of each word.
The Transfer Complete Flag is specified for the Master mode only.
I have been testing it and the the flag does not get set in the Slave mode.
You can use DMA for the LPSPI Slave.
But this is really application-dependent, there is no simple answer I'm afraid.
Regards,
Daniel
Hi @yfliu,
Before the LPSPI_PCS input asserts, the transmit FIFO must be filled with transmit data, or the transmit error flag will set.
The data match function can be used though,
RM, rev.12.1, Section 51.4.3.2 Receive FIFO and Data Match.
Data match interrupt can be enabled on assertion of the MDF flag which indicates that the received data has matched the MATCH0 and/or MATCH1 fields (as configured by CFGR1[MATCFG]).
And the data match interrupt routine can fill the FIFO with new data.
Regards,
Daniel
Thanks for the prompt reply! Would you please further clarify:
It will be great if you can share some keypoints of handling data match in ISR.
Regards,
yf
Hi @yfliu,
I'm sorry for the delayed response,
Regards,
Daniel
Thanks a lot!
We have 8 bits per frame in ProcessorExpert for our LPSPI, thus we expect the DMR will happen right after the first byte is xferred.
It will be nice if you can share where I can find explanation for terminologies such as FRAME, WORD, TRANSFER etc. It seems in the LPSPI status register has `Frame complete`, `Word complete` and `Transfer complete status` respectively, but I hardly can find any explanation on these concepts.
My intention is to balance between flexibility and performance: 1) number of ISR occurances shall be small so that to reduce MCU load, 2) response to a few commands shall be instant (majority commands can be handled in best effort manner).
Also I am wondering if we can use DMA mode for LPSPI, then have at most two ISR occurances for each transaction --- one after the first byte (checking commands), the other upon end of the transaction. Not sure if this is feasible?
Hello @yfliu,
Yes, the match interrupt asserts after the first 8bit frame is received if the data match.
Regarding WORD / FRAME side, I think it is explained in the description of the FRAMESZ register.
The Frame Complete Flag (FCT) asserts when the frame is complete which can consists of many words.
Whereas the Word Complete Flag (WCF) asserts on completion of each word.
The Transfer Complete Flag is specified for the Master mode only.
I have been testing it and the the flag does not get set in the Slave mode.
You can use DMA for the LPSPI Slave.
But this is really application-dependent, there is no simple answer I'm afraid.
Regards,
Daniel
@danielmartynek , many thanks for the nice explanations.
So it seems that apps can define frame size explicitly, but word size is defined by the LPSPI module implicitly?
Hi @yfliu,
Yes, the frame size can be selected in the FRAMESZ register.
The word size (max. 32 bits) depends on the frame size and the position of the word in that frame.
Regards,
Daniel