Use S32K1xx as responsive SPI slave

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Use S32K1xx as responsive SPI slave

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yfliu
Contributor III

Hi,

I am considering to use S32K1xx to implement a very responsive SPI slave which can response to within the same SPI command transaction.

Supposes that:

  • The commands from SPI master are 1-byte long.
  • The SPI transaction is always 4 words long.

There is one perticular command needs quick response, better within the same transaction.

How to program the S32K1xx MCU to achieve this? Can LPSPI do the job?

Best regards and thanks in advance!

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @yfliu,

Yes, the match interrupt asserts after the first 8bit frame is received if the data match.

Regarding WORD / FRAME side, I think it is explained in the description of the FRAMESZ register.

danielmartynek_0-1618240227020.png

The Frame Complete Flag (FCT) asserts when the frame is complete which can consists of many words.

Whereas the Word Complete Flag (WCF) asserts on completion of each word.

The Transfer Complete Flag is specified for the Master mode only.

danielmartynek_1-1618240530752.png

I have been testing it and the the flag does not get set in the Slave mode.

 

You can use DMA for the LPSPI Slave.

But this is really application-dependent, there is no simple answer I'm afraid.

 

Regards,

Daniel 

 

 

 

 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @yfliu,

Before the LPSPI_PCS input asserts, the transmit FIFO must be filled with transmit data, or the transmit error flag will set.

The data match function can be used though,

RM, rev.12.1, Section 51.4.3.2 Receive FIFO and Data Match.

Data match interrupt can be enabled on assertion of the MDF flag which indicates that the received data has matched the MATCH0 and/or MATCH1 fields (as configured by CFGR1[MATCFG]).

And the data match interrupt routine can fill the FIFO with new data.

 

Regards,

Daniel

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yfliu
Contributor III

@danielmartynek ,

Thanks for the prompt reply! Would you please further clarify:

  • Data matching must happen after 32-bit word is transferred, right? my case is single byte (8-bit) matching for single byte command. I need set CFGR1[MATCFG] as 110b with MATCH1=0xFF and MATCH0=[command]?
  • Note that a SPI transaction is 4 words (16B) in my case. When data match interrupt happens, the ongoing transaction should have already finished the 1st word, we only need write our reply word to TDR register and it will be transferred out immediately in the same transaction? as the FIFO is 4 words in total, which word in the FIFO will carry the answer data?
  • Can data match feature work with DMA mode? 

It will be great if you can share some keypoints of handling data match in ISR.

Regards,

yf

 

 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @yfliu,

I'm sorry for the delayed response,

  • You can select Match configuration (MATCFG) that suits your application. But it does not need to receive a 32bit frame - it depends on the selected frame size (FRAMESZ). So, for example, if you use 8bit frames, you need to write 8bit word(s) into the data match registers and it will compare it to the 8bit frame that it receives.
  • The transfer driven by the master does not stop, so there must be some data in the TX FIFO before the transfer starts. This depends on the core clock, interrupt priority, SPI bitrate.. The FIFO is 4-words long but the first word (8bit) is already shifted out when the first 8bit frame is received by the slave, and you can always read the TX FIFO status in the interrupt handler (FSR_TXCOUNT).
  • You don't have to use this data match feature, you can simply process the received data in the handler - this will add some processing time.
  • Unfortunately, the MCU does not support DMA request on the SPI Data Match.

danielmartynek_0-1617891378720.png

 

Regards,

Daniel

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yfliu
Contributor III

@danielmartynek 

Thanks a lot!

We have 8 bits per frame in ProcessorExpert for our LPSPI, thus we expect the DMR will happen right after the first byte is xferred.

It will be nice if you can share where I can find explanation for terminologies such as FRAME, WORD, TRANSFER etc. It seems in the LPSPI status register has `Frame complete`, `Word complete` and `Transfer complete status` respectively, but I hardly can find any explanation on these concepts. 

My intention is to balance between flexibility and performance: 1) number of ISR occurances shall be small so that to reduce MCU load, 2) response to a few commands shall be instant (majority commands can be handled in best effort manner).

Also I am wondering if we can use DMA mode for LPSPI, then have at most two ISR occurances for each transaction --- one after the first byte (checking commands), the other upon end of the transaction. Not sure if this is feasible? 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @yfliu,

Yes, the match interrupt asserts after the first 8bit frame is received if the data match.

Regarding WORD / FRAME side, I think it is explained in the description of the FRAMESZ register.

danielmartynek_0-1618240227020.png

The Frame Complete Flag (FCT) asserts when the frame is complete which can consists of many words.

Whereas the Word Complete Flag (WCF) asserts on completion of each word.

The Transfer Complete Flag is specified for the Master mode only.

danielmartynek_1-1618240530752.png

I have been testing it and the the flag does not get set in the Slave mode.

 

You can use DMA for the LPSPI Slave.

But this is really application-dependent, there is no simple answer I'm afraid.

 

Regards,

Daniel 

 

 

 

 

 

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yfliu
Contributor III

@danielmartynek , many thanks for the nice explanations.

So it seems that apps can define frame size explicitly, but word size is defined by the LPSPI module implicitly? 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @yfliu,

Yes, the frame size can be selected in the FRAMESZ register.

The word size (max. 32 bits) depends on the frame size and the position of the word in that frame.

 

Regards,

Daniel

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