Unable to exit from VLPS mode to RUN with watchdog enable

[KKumar]

Hi NXP,

Following code working fine in transition from RUN to VLPS and from VLPS to RUN

KKumar_0-1683371688097.png

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After adding watchdog disable before Low mode entry and enable watchdog at exit, it is working fine from RUN to VLPS but not exit from VLPS on interrupt

KKumar_1-1683371828120.png

Help me to solve the issue

[KKumar]

Hi @Senlent 

One more doubt i have..
I am disabling FIRC source in "stop_mode_config"  function which is the source of MCU Core.

Means, now there is no CORE CLK  then how below (below "stop_mode_config")function are getting executed  by MCU and  putting itself in stop. mode.

[Senlent]

Hi@KKumar

the SIRC will be the source of the system clock.

27.4.4 VLPR/VLPS mode entry
When entering VLPR/VLPS mode, the system clock should be SIRC. The FIRC, SOSC,
and SPLL must be disabled by software in RUN mode before making any mode
transition.

[Senlent]

Hi@KKumar

please check bit CS->UPDATE .

Senlent_0-1683516643876.png