UCANS32K1SIC: Default ISR triggers at random instances when trying to receive frames using Rx FIFO

[Shubha_Ravi]

Hello,

I am trying to implement CAN communication on S32K146, Reception using FIFO and Transmission using buffer method. Since the code cannot be shared, I would like to explain my application workflow in order to make you understand, so that you can guide me if I am missing something.

1. I have a set of CAN frames which are periodically sent on CAN bus at different time intervals (eg. 100ms, 200ms, 1000ms and so on)

2. I also receive some CAN frames which are periodically sent by a different controller. (this is simulated using PCAN)

3. When we receive some CAN frames, we need to send out certain Tx frames as a response.

In order to achieve this, I have used Tx buffer method and Rx FIFO (interrupt based) method example provided by NXP.

The above-mentioned 1st point works seamlessly. But the issue seems to be while receiving frames i.e. after receiving frames for certain time (which is not same always), it triggers default ISR for which the cause is unknown because each time the code halts at a different function.

Could you please help us to understand how this can be resolved. Could there be a possibility of any internal buffer overflow at the lower levels?

Best Regards,

Shubha Ravi

[Shubha_Ravi]

Hello Team,

It would be great if I can get some input on this issue. We have a software delivery planned in the coming weeks