UART clock issue using Tresos - S32K344

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UART clock issue using Tresos - S32K344

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MVR
Contributor V

Hello everyone,

I'm configuring the UART peripheral on Tresos tool as per AUTOSAR standard for S32K344 uC.

With my clock configuration (mcu module), the message is out of baudrate selected. If I use the example project, it works fine.

Can you please help me with this topic? What is the configuration that I'm doing wrongly?

Spec. Version: 4.7.0

SW Version: 4.0.0 HF01_D2401

Attached are the both mcu modules configurations (one of them work fine, from example project).

Also I attached the UART module configuration that is very simple.

Note: In my configuration, I'm using PLL.

Thanks,

MVR

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Robin_Shen
NXP TechSupport
NXP TechSupport

Sorry, I may not understand your question. If you follow your settings, the UART baud rate observed by a logic analyzer or oscilloscope is not 115200?

From your Uart.xdm, I see that you use LPUART0. According to Table 124. LPUARTn instance clocking of the S32K3 reference manual: LPUART [0] and [8] is clocked by AIPS_PLAT_CLK.
AIPS_PLAT_CLK has been configured to 40MHz.
In your Mcu.xdm, PLL_PHI0_CLK is selected as the CGM0 Clock Mux0 Source.

And Uart_Example_S32K344 uses LPUART3: LPUART [1:7] and [9:15] is clocked by AIPS_SLOW_CLK.
AIPS_SLOW_CLK has been configured to 24MHz.
FIRC_CLK is selected as the CGM0 Clock Mux0 Source.

Do you call Mcu_DistributePllClock after calling Mcu_InitClock?


Best Regards,
Robin
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Robin_Shen
NXP TechSupport
NXP TechSupport

Sorry, I may not understand your question. If you follow your settings, the UART baud rate observed by a logic analyzer or oscilloscope is not 115200?

From your Uart.xdm, I see that you use LPUART0. According to Table 124. LPUARTn instance clocking of the S32K3 reference manual: LPUART [0] and [8] is clocked by AIPS_PLAT_CLK.
AIPS_PLAT_CLK has been configured to 40MHz.
In your Mcu.xdm, PLL_PHI0_CLK is selected as the CGM0 Clock Mux0 Source.

And Uart_Example_S32K344 uses LPUART3: LPUART [1:7] and [9:15] is clocked by AIPS_SLOW_CLK.
AIPS_SLOW_CLK has been configured to 24MHz.
FIRC_CLK is selected as the CGM0 Clock Mux0 Source.

Do you call Mcu_DistributePllClock after calling Mcu_InitClock?


Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

 

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MVR
Contributor V

Hello @Robin_Shen 

I was not calling Mcu_DistributePllClock, now it is working. Thank you

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