Issue Description:
ADC0 sampling by PDB0 is triggered by FTM2, and ADC1 sampling by PDB1 is triggered by FTM3.
The PWM frequency of FTM2 and FTM3 is set to 10 kHz.The FTM module is clocked at 80 MHz and configured in symmetric up-down counting mode
ADC0 has 4 channels and ADC1 has 5 channels, with triggering implemented in a back-to-back mode.
Sampling works normally when ADC hardware averaging is disabled, but becomes abnormal when 4-sample hardware averaging is enabled.
The ADC0 clock is configured to 40 MHz with a short sampling time, which should not affect PDB triggering. Additionally, FTM triggering is disabled in the ADC interrupt and re-enabled in the PDB interrupt.
Furthermore, ADC interrupt-based data acquisition works when breakpoints are set during debugging, but fails to run under continuous operation.
Could the conflict between PDB1 and PDB0 acquisitions be the root cause?
My questions are as follows:
- Both FTM2 and FTM3 are set to 10 kHz and used to trigger PDB0 and PDB1 respectively. If there is a conflict in the ADC completion interrupts, could this cause sequence errors in the PDB?
- Are there any precautions for the PDB triggering mode when using ADC hardware averaging?
- Why can the ADC interrupt be entered and acquisition data be obtained when breakpoints are set during debugging, but the ADC interrupt cannot be entered during full-speed operation? How should debugging be conducted in this case?
- During debugging, the configuration of 4-sample hardware averaging for the ADC can basically be completed within 1000 PDB CNT cycles, so it should also be completed within 8000 PDB CNT cycles.
