I have problem with interrupt of DMA on TX LPSPI1.
I want that interrupt of DMA to set after transfer from memory to SPI-TX.
Every 100 ms my programm set a pin CS to LOW and at once begin DMA0_Transmit (transmit 4 bytes). And after I wait IRQ.
For this I set DMA->TCD.CSR |= DMA_TCD_CSR_INTMAJOR(1);
But interrupt set at once, before SCK transmit.
S32_NVIC->ICPR |= 1 << (0 % 32); // IRQ0-DMA channel 0 transfer complete: clr any pending IRQ
S32_NVIC->ISER |= 1 << (0 % 32); // IRQ0-DMA channel 0 transfer complete: enable IRQ
S32_NVIC->IP |= (0x0D << 3); // IRQ0-DMA channel 0 transfer complete: priority 13 of 0-15
DMA->CINT = DMA_CINT_CINT(0);
PTB->PTOR |= 1 << PTB17;
it could be normal behavior, I think. DMA is writing to the LPSPI TXFIFO (up to 4 words) so if it is empty DMA write is finished much sooner than actual SPI transmit on the bus.
Try to generate Frame complete interrupt from LPSPI.
I noticed that the interrupt is always two bytes late. Therefore, I add an additional two bytes every time I send. But me interested how to do it correctly using only DMA without interrupt of the SPI?
even if you have TXWATER=0, you have 1deep TXFIFO and shift register, thus after 2nd byte is transmitted, 3dr byte in TXFIFO moves to shift register and DMA can store last byte to TXFIFO, so you get DMA major interrupt.
Hi Timur, could you check whether the optimization level of your project is set to 1 or above? I have met a similar situation when using LPUART while the optimation level of the SDK is set to 1. After changed to 0, never happened again.