SPI communication with interrupts disabled

[mahesh09]

Hi, In S32K146 we use LPSPI to communicate with an external device. In a 20us interrupt, we start the SPI communication by writing to TDR register and in the next 20us interrupt cycle we read data from FIFO register and start SPI communication again and the cycle repeats. This sequence works without any issues.

Under certain condition I have to disable all interrupts to perform critical function for ~5msec. When I re-enable the interrupts, 20us interrupt fires as expected. But sometimes no data will be available in the FIFO. Further investigation shows data becomes available in the FIFO after a while.

Does disabling the interrupts (cpsid) freeze SPI communication. As we are not using interrupts and polling for the results, I was expecting SPI communication to continue and results to be copied to FIFO register even when interrupts are disabled.

Thanks.

[mahesh09]

Sorry, I was not clear in my query. Disabling of interrupts is done in background task, so SPI communication will be started in the 20us interrupt. My question is should not SPI communication continue even when interrupts are disabled and SPI data be available in FIFO?

[danielmartynek]

Hello @mahesh09,

Yes, the LPSPI module works when the interrupts are masked, whatever was placed in the TC FIFO will be sent and the LPSPI module will receive data at MISO.

To debug the issue, toggle a GPIO in the 20us interrupt and scope the SPI bus.

BR, Daniel

[danielmartynek]

Hi @mahesh09,

When the interrupts are masked (cpsid), any triggered interrupt becomes pending in NVIC.

Once they are unmasked, they will become active depending on their priority, and this is asynchronous to the 20us trigger.

So, you can have two such interrupts in a period shorter than what the SPI transfer takes.

Can you disable the 20us trigger before the interrupts are masked globally?

Thanks,

BR, Daniel