Hello NXP,
When I checked the SPI clock in Salae. It was not uniform (Attached image for reference). I expected the clock to be in 50% duty cycle but instead I got a clock with varying duty cycle.
Our microcontroller is NXP S32K358. I am using LPSPI_4. The baud rate is 2MHz.
Hi @Guna,
Are there any errors caused by the duty cycle? From the slave point of view, this is should not be an issue since SPI transmission is driven by CLK edges (with asserted CS).
I believe the varying duty cycle is aliasing caused by the logic analyzer since the logic analyzer is good for capturing the SPI signal, but it is not suitable to judge clock stability. You can use a scope triggered on one edge to see the stability of the other edge and a calibrated frequency counter to check the absolute frequency.
You can look at Table 428. (Timing parameters) from S32K3xx's Reference Manual for the LPSPI's timing values:
Duty cycle is the difference between SCKSET and SCKHLD.
There is an example configuration for 10MHz with 50/50 duty cycle under the table:
The SPI_Transfer_S32K344/S32K358 examples have a 100kHz frequency with 50% duty cycle:
Best regards,
Julián
