SPI CLK WaveForm

[Embedded_novice]

我想知道为什么SPI通信中每发送一个字节，CLK的波形都会变短一下。我尝试将频率从500K修改为1M，这种情况会好一些，但依然会有这种现象。

[PavelL]

Hi,

Could you share a waveform with all SPI signals? What processor are you using?

It still could be a correct behavior, it might be related only to SPI settings.

Best regards,

Pavel

[Embedded_novice]

我使用的是S32K116，它实际上不会影响我的通信，但是我是想知道为什么会发生这种现象？我无法提供全部的波形图，抱歉。

[PavelL · Accepted solution]

Hi,

your CLK is negative = active low, it means that inactive level is high. When PCS goes high, the clock goes to the inactive level. If there is a short positive pulse on PCS (= short delay between frames), the CLK might be the short pulse you can see now.

Best regards,

Pavel

[Embedded_novice]

但是我依然有一个问题，我在传输完8个字节数据前是没有执行CS拉高的GPIO操作的，但是他依然会出现这种情况？

[PavelL]

Hi,

at first, please check your clock settings. Your frame length 8usec (estimated from your waveform) doesn't correspond to the "Baudrate 500000". I would expect frame rate 16usec/frame for 8 bit frame. "Source clock 16000000" needs to be manually synchronized with your settings in Peripheral clock view in S32DS.

Next item, there is no PCS settings in SDK. So, it needs to be manually setup by LPSPI_DRV_MasterSetDelay

Personally, I prefer working PCS. It might show settings issues.

Best regards,

Pavel

[Embedded_novice]

感谢你的帮助