SAI0 in transmit mode as a bitclock slave and frame sync slave

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SAI0 in transmit mode as a bitclock slave and frame sync slave

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sebastian_wozni
Contributor III

Hello

Does anyone know if SAI0 in transmit mode can be configured as bit clock slave and frame sync slave?

Regards,

Sebastian

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19 Replies

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian Wozniak

Yes, the transmitter can receive the bit clock and the frame sync from the Master device (which in this case is the receiver) and there should not be any issue. For your reference I recommend you the following AppNote:

https://www.nxp.com/docs/en/application-note/AN12202.pdf 


Have a great day,
TIC

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sebastian_wozni
Contributor III

Hi Jorge!

Thank you for your reply.

Unfortunately in my configuration when I use SAI0 as the transmitter slave, SAI doesn't recognize correct frame sync.

In the same time SAI1 with the same frame sync and bit clock configured as a receiver - slave is working correctly.

Below I attached screenshots from Saleae.

Screenshot from 2019-06-24 11-25-16.png

Screenshot from 2019-06-24 11-12-04.png

Screenshot from 2019-06-24 11-10-00.png

I measured bit clock with analog oscilloscope and its frequency is 12.288 MHz

Regards

Sebastian

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linhnguyenhoang
NXP Employee
NXP Employee

Hello Sebastian,

I need some information:

- Do you use SAI S32 SDK driver ?

- If yes do you generate configuration using processor expert ? It has GUI like this:

support_sai_community.png

From your information that same configuration works correctly on SAI1 instance, I guess that it may have something to do with pin or dma. 

- Can you verify that pins is working correctly by:

   Putting data pin in GPIO output mode, then toggle it and see if there is any signal

   Putting frame sync and bit clock pin in GPIO input mode, apply signal and see if there is any change in pin values

- I see FRDE bit is 1, are you using DMA ? Did you setup dma correctly, SAI0 and SAI1 use different DMA request

- Can you try again with lower bit clock frequency and see if it works ?

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sebastian_wozni
Contributor III

Hi Linh!

Thank you for your reply.

- No I'm not using SAI S32 SDK driver. I'm using my own driver.

In my previous post I mention that SAI1 worked correctly with the same frame sync and bit clock but configured as a receiver - slave.

- I've checked all pins in GPIO mode and they are working correctly.

- Yes, FRDE bit is set 1 because I'm using DMA. DMA is set correctly cause it is working on different board as bit clock master and frame sync master.

- I've tried with lower bit clock frequency but still it doesn't work.

One additional information that when I've set bit clock slave and frame sync master, then DMA is working correctly but generated frame syncs are too frequent.

Best regards,

Sebastian

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian Wozniak

It is difficult to replicate your issue in our side as long as we don't have the full configuration of the module. I have successfully configured the SAI0 as the transmitter in Slave mode, so the clock is actually received by the SAI1 (which is configured in the receiver as master).

In order to do this, I used the example code of the SDK, and with the processor expert tool, I change for the configuration that I mentioned:

pastedImage_1.png pastedImage_2.png

I would recommend trying this configuration with the SDK first so we can discard any problem with the DMA or with the drivers that you are using.

Best regards

Jorge Alcala

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sebastian_wozni
Contributor III

Hi Jorge Alcala!

As addition I've checked one more scenario I've changed Sync direction to Internal and I've unplugged WM8960 frame sync and like previously counter stops at 66 and frame sync was to frequent as on screenshot below.

Screenshot from 2019-07-24 10-05-19.png

I'm attaching source code which I've used to check scenarios from this and previous answer.

If it's possible I'd like to check your configuration. Can you share with me block schematics from your setup?

Best regards,

Sebastian

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian Wozniak

I saw that you have 1 in sync width, If you are using I2S standard protocol, you should have this value with the width of your data frame, in my case I used with 16 bits. Please see below my full configuration:

pastedImage_1.png

Hope this could help you.

Regards

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sebastian_wozni
Contributor III

Hi Jorge Alcala!

Sync width was 1 because I'm using DSP mode not I2S. But just to be sure I've checked your configuration with I2S protocol, once with 16 bit then with 32 bits and in both data didn't appear. Screenshots below are referring to 16 bit configuration.

Screenshot from 2019-07-26 14-29-55.png

Screenshot from 2019-07-26 14-30-10.png

I've also checked your configuration from the previous answer and then I've checked mine (sceenshot below) which is the same as in my driver but like in other configurations data just don't want to flow.

sai0(3).png

Screenshot from 2019-07-26 11-37-08.png

By the way can you tell me which Design Studio you're using because you have one different option, you have option called "Mode" and I have "Bit clock direction" and "Sync direction" instead. Is it any difference between that? I attach my Design Studio configuration.

Best regards,

Sebastian

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian Wozniak

I'm using "S32DS ARM 2018 R1" with the SDK 3.0 RTM, I believe the different I2S configuration is not related with the IDE but with different SDK, did you update the software in your IDE?

Could you first try to use the example with the SAI0 and SAI1, I would like to discard any problem with the codec that you are using, as I mentioned, I only import the example SAI from the SDK 3.0 RTM and I change it so the transmitter receives the clock and the frame sync externally:

pastedImage_2.png

I'm able to see that the clock and the frame sync are generated by the SAI1 and the output data is send by the SAI0 (only with the external signals). I didn't modify anything in the main file, so there is no need to attached.

pastedImage_1.png

pastedImage_2.png

Regards

Jorge Alcala

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sebastian_wozni
Contributor III

Hi Jorge Alcala!

I've checked this example and it worked. So with this knowledge I've started looking for problem with my driver and by mistake I've found electrical problem which was cause by me. Now everything is working correctly so I would like to thank you for your support, I really appreciate that!

Best regards,

Sebastian Wozniak

241 Views
sebastian_wozni
Contributor III

Hello Jorge Alcala!

I've tried your suggestion so I've generate example code from the SDK but I took clock from WM8960 instead of receiving clock from SAI1 and it still doesn't work. To check data flow I wrote function with counter and with configuration as on screenshots below counter was always 0 but when I've change Sync direction to Internal then counter starts count but only till 66 and while data occurred frame sync was too frequent.

sai0.png

sai0(2).png

Screenshot from 2019-07-23 18-40-29.png

Best regards,

Sebastian

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian Wozniak

How are you configuring BCD in the TCR2, as I understand, you wan to configure the SAI0 as transmitter with the bit clock generated externally, am I correct?

Also, please check the following note in the reference manual:

Before using SAI_TX_DATAx (SAI_Dx), SAI_SYNC, or
SAI_BCLK for input configurations, GPIO_PDDR must be
configured for the corresponding pins.

Regards

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sebastian_wozni
Contributor III

Hi Jorge Antonio Alcala Vazquez!

Are there any updates?

Regards,

Sebastian

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian Wozniak

Could you share your code or the SAI config part?, it would be easier to look for the source of the issue if I can reproduce the issue in my side.

How are you configuring the Bit Clock Input (BCI) in the same TCR2 register? If you set this bit the "Internal logic is clocked as if bit clock was externally generated"

Best regards

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sebastian_wozni
Contributor III

Hi Jorge Antonio Alcala Vazquez!

Unfortunately I can't share my code but I will show you SAI0 register setup.

Screenshot from 2019-07-02 11-04-49.png

Screenshot from 2019-07-02 10-58-15.png

Screenshot from 2019-07-02 10-58-31.png

Maybe helpful information will be that in my configuration TDM master is WM8960.

Best regards,

Sebastian

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Sebastian

Did you try with the BCI bit set in your tests? I don't see it set in the images that you attached. Also, please consider the following note of the Reference Manual.

To correctly generate the SAI’s internal bit clock when
TCR2[BCI] bit is set, TCR2[SYNC] must be set to 0x01 in
either receiver or transmitter configuration.

Regards

Jorge Alcala

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sebastian_wozni
Contributor III

Hi Jorge Antonio Alcala Vazquez!

 

Are there any updates?

 

Regards,

Sebastian

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sebastian_wozni
Contributor III

Hi Jorge Antonio Alcala Vazquez!

In my configuration bit clock is generated externally by WM8960, so according to Reference Manual "This field (BCI) has no effect when configured for an externally generated bit clock.", that's why I didn't setup BCI.

But just to make sure I've tried out your idea with setting up BCI and SYNC but unfortunately it didn't work out neither.

Screenshot from 2019-07-04 12-44-46.png

Regards,

Sebastian

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sebastian_wozni
Contributor III

Hi Jorge!

Yes, you are correct. I am trying to configure the SAI0 as transmitter with the bit clock generated externally, this is why I configured BCD in the TCR2 as slave so value in that register is 0x0.

I am not configuring GPIO_PDDR but I have checked this register and its value is also 0x0 so as in reference manual this mean GPIO is configured correctly as input.

Regards,

Sebastian

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