S32k314 Power up and Power down sequencing

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

S32k314 Power up and Power down sequencing

805 Views
ajnas-c
Contributor I

Hi,

Anyone please let me know the recommended S32k314 Power up and Power down sequencing timing diagram.

VDD_HV_A, VDD_HV_B, V15, V11, V25

 

Regards,

Ajnas

0 Kudos
Reply
3 Replies

795 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

The device keep MCU in POR reset in any of used voltage is below LVR level (1.1V, 2.5V, VDD_HV_A and VDD_HV_B) so basically there is no power sequencing defined.

MCU will leave POR state when all the POR sources clear.

 

0 Kudos
Reply

792 Views
ajnas-c
Contributor I
My question is, which voltage needs to come first to the MCU, when we power the S32K314?
Are there any timing requirements, all voltages come first, is there any problem?
Please clarify the same.
0 Kudos
Reply

783 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

There is only defined ramp rate and a monotonicity requirement but no power rail ramp ordering or differential voltages between power rails is defined so it should not matter. LVD circuits keep the device in the safe state (i.e. in reset) until all voltage rails are valid.

davidtosenovjan_0-1673437367198.png

 

davidtosenovjan_1-1673437435800.png

 

 

0 Kudos
Reply