S32K3X8EVB-Q289 rework for RMII

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S32K3X8EVB-Q289 rework for RMII

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ssattva1
Contributor III

Hello , I am currently working on S32K3X8EVB-Q289 for ethernet implementation. 

I was going through the hardware user manual and came across the section "rework for rmii"

ssattva1_0-1736233303141.png

As per this table , i made the necessary changes in the board. 
However , after making the changes lwip baremetal example was not working . Ping test was not working as well. Moreover , I have another eval board without making the above mentioned hardware changes. That one works fine . 

What could be the reason that the first board with hardware changes fails.? Why is this rework for rmii needed if lwip example can work even without these changes ?

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PavelL
NXP Employee
NXP Employee

Hello @ssattva1 ,

I think that it is correct.

Default pin mapping of example lwip_baremetal_s32k358 is RGMII, but GMAC is set to RMII. That's why it works without changes.

If you do RMII rework, you should change GMAC's pin mapping as well.

Best regards,

Pavel

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ssattva1
Contributor III

Hi @PavelL 

You mentioned that I have to change the GMAC pin mapping if I am reworking the eval board for rmii.

ssattva1_0-1736332905818.png

It was XMII initially. Should I change it to XGMII ? Is that what you mean? If not what should I change exactly?

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PavelL
NXP Employee
NXP Employee

Hello @ssattva1 ,

I double checked pin mapping of example lwip_baremetal_s32k358 together with schematics of S32K3X8EVB-Q289 and ADTJA1101.

In my opinion:

  • No SW changes are necessary - RX_ER is not assigned in Gmac to pins, RX_DV (PTC16) and TX_EN (PTE9) are assigned to pins
  • HW changes shall look like that, i.e. the highlights are valid:

PavelL_0-1736408123487.png

Please check it out.

Best regards,

Pavel

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ssattva1
Contributor III

So is it enough if I just follow the highlighted changes ? The GMAC should still be in RMII mode right?

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PavelL
NXP Employee
NXP Employee

Hello @ssattva1 ,

Yes, I think so, because ADTJA1101 works on RMII mode only.

Best regards,

Pavel

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ssattva1
Contributor III

Hi @PavelL ,

So this is the pin mapping that i have currently , the default mapping that comes along with the example. 

ssattva1_0-1736332332943.png

I am flashing this configuration in a board with no rework for rmii . I probe the txctl and tx_en signals , which are at PTB25 and PTE9 respectively. I observed that TXCTL goes high whenever i transmit a frame , but when i observed tx_en from PTE9 I obsrved this

ssattva1_2-1736332491045.png

A periodic pulse of period 80ns .  
What I infer is , tx_ctl essentially acts as the tx enable signal. Also in schematic Tx_ctl line is populated and tx_en from PTE9 is DNP. Then what is this periodic signal from PTE9 that I am observing.

 

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ssattva1
Contributor III

@PavelL  kindly clear this query

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ssattva1
Contributor III

Hi @PavelL could you elucidate on what pin mapping changes should i do if i use the rework for rmii? Is changing the MII mode to RGMII in the peripherals perspective enough or should I do something else

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ssattva1
Contributor III
NOTE: I am using ADTJA1101 board for PHY. It is RMII configured
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