S32K344 The CMP input level is higher than the comparison level until the interrupt is entered.

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S32K344 The CMP input level is higher than the comparison level until the interrupt is entered.

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dingyazhou1
Contributor I

CMP always enters the interrupt at high level, and after clearing the interrupt flag, it enters the interrupt again, and both the upper and lower edge interrupt and the interrupt flag with different values exist. CSR is 0x07. According to the manual, under normal circumstances, the interrupt should be terminated after one interrupt, and the predefined value should be updated

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