S32K344 QSPI clock change to 100MHz high frequency and DLL configuration

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S32K344 QSPI clock change to 100MHz high frequency and DLL configuration

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Li_Chen
Contributor III

My project is based on Fls_Example_S32K344 from S32DS IDE, I'm using QSPI to connect with external flash. The QSPI bus works fine for 48MHz QSPI clock. The device ID read back is 0x2C, 0x46 for two bytes as expected. However, after I increase the clock to 100MHz, I got 0x58, 0x8C. It seems the first bit get lost. After further check RM, I changed DLY coarse from 4 to 2, Tap select from 4 to 2 and enable DLL high frequency operation, and then I got correct read back. I carefully review the DLL bypass mode in RM but still don't quite understand those parameters.

qspi_setting.png

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I have found application note where section

3.3.3. DLL and DQS delay chain

explains this setup a bit clearer way:
https://www.nxp.com/docs/en/application-note/AN13563.pdf

However I will investigate it further and return to you.

 

 

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