S32K344 - LPSPI and DMA configuration

[il_ciancio]

Hello to all NXP experts!

I am starting to develop an SPI communication in loopback on my EVK.

Is there any example with SPI configured with  DMA for Tx and Rx (for both Master and Slave)?

Thanks a lot!

[il_ciancio]

Hi @VaneB,

I have done a little step, attached you will find a configuration were (I will update also for the other users):

• LSPI2 is master with DMA;
• LSPI0 is slave with DMA;
• the description is updated with "new" wired connection.

Now I am able to trasmit and receive data between the channels with the API Lpspi_Ip_AsyncTransmit.

The first trasmission works correctly, when a I try to send again data, I will not see that the buffers are updated.

Debugging, I am reaching the DMA RX interrupt, but the RAW data are not "updated".

Any idea?

Thanks.

[VaneB]

Hi @il_ciancio 

I have tested your code and have some observations. First, the S32K3 SPI Driver Integration Manual states that in DMA transfer mode, DMA transfers may cause cache coherency problems. To avoid possible coherency issues when D-CACHE is enabled, ensure that the buffers used as TCD source and destination are allocated in the NON-CACHEABLE area (using Spi_Memmap).

Regarding the buffer update problem, please test the following example code and let me know if you observe the same behavior. Note that this application uses the LPSPI driver to transfer data between LPSPI2 (master, no DMA) and LPSPI0 (slave, with DMA). Although both are not using DMA, this will help us verify the behavior.

NOTE: The example code was developed using RTD 5.0.0 and S32DS 3.5. We always recommend using the latest software and tool versions.

[il_ciancio]

Hello @VaneB,

sorry for the late reply.

I have updated as you suggested my RTD, and I have imported  

• Lpspi_Ip_Transfer_S32K344.zip.

I have specialized a little bit your code and with the Lpspi_Ip_SyncTransmit I am able to send again data.

Regarding:

I have tested your code and have some observations. First, the S32K3 SPI Driver Integration Manual states that in DMA transfer mode, DMA transfers may cause cache coherency problems. To avoid possible coherency issues when D-CACHE is enabled, ensure that the buffers used as TCD source and destination are allocated in the NON-CACHEABLE area (using Spi_Memmap).

I have added SPI_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE pragma between my buffers, but something changes.

Attached you will find the project. I have configured DMA for both LSPI channel, and I am working in interrupt mode for both channel. I am using Lpspi_Ip_AsyncTransmit because of DMA.

The first exchange between Master and Slave works correctly only for the SLAVE, the MASTER hasn't received correctly all the data.

.

After I clean the buffers, I am sending new data, but I have the same behaviours: the rx master buffer doesn't cotain all data. As I increase the data of the buffer as the lost data is increased.

Any idea?

Thanks a lot!

•  

[VaneB]

Hi @il_ciancio 

I believe there is a misunderstanding regarding the frame size you are assigning when calling the Lpspi_Ip_UpdateFrameSize() function. This value corresponds to each data length, not the number of data items you are transmitting. According to the TxBuffers FrameSize parameter, the function Lpspi_Ip_UpdateFrameSize() should be set to 8 instead of the 32 you are currently assigning.

Regarding your code, since the issue seems to be only from the master, I made a test by disconnecting the Slave pins and connecting the Master pins in a hardware loopback configuration (Master output connected to Master input). Please test this modified project on your side.

[il_ciancio]

Hi @VaneB,

thanks to your suggestions I have done multiple messages exchange between LSPI0 and LSPI2, full duplex and with DMA, so thanks a lot, great job!

I have a question about:

According to the TxBuffers FrameSize parameter, the functionLpspi_Ip_UpdateFrameSize()should be set to 8 instead of the 32 you are currently assigning.

1) why can not I use 32 as frame size? Looking the configuration the max value could be 64 (now it is 64, I want to show you what i mean).

.

2)The API Lpspi_Ip_AsyncTransmit has as parameter Length "number of bytes to be sent", but It seems that It is used also as Rx side, not only for Tx side.

I have done an excercise where Master sends 1024 and receives 8, slave sends 8 and receives 1024, during the execution, the Master is always in BUSY status.

Any opinion on that?

3) Why is there not an API/Driver only for receive (as slave) and only for send data (as master)?

It is attached also my project, maybe should be usefull for other users (RTD 5.0.0, S32D 3.5). In the project there are also the defines to test question 2.

Thanks!

[VaneB · Accepted solution]

Hi @il_ciancio 

I wanted to clarify my previous comment. My focus was on the implementation of your code. As you mentioned, the frame size can indeed be assigned up to 64.

I apologize if my earlier message was not clear. Thank you for bringing this up.

Regarding your second question, as you correctly noted, the Length parameter of the Lpspi_Ip_AsyncTransmit() function is used for both transmission and reception. Therefore, if you send less data than expected to be received, the master or the slave will remain in a waiting state until all the expected data is received.

[il_ciancio]

Thanks for the support,

I will close this topic. For the third question I think the answer is the Half Duplex mode, where we can specify the sender and the receiver.

Thanks a lot!

[VaneB]

Hi @il_ciancio 

There is not a specific example code for SPI master and slave using both DMA, but the following examples might be useful:

• Example S32K344 SPI Transmit & Receive Using DMA DS3.5 RTD500: This application uses the LPSPI driver to transfer data between LPSPI2 (master, no DMA) and LPSPI0 (slave, with DMA) physical units.
• Example S32K312 SPI Transmit & Receive Using DMA DS3.5 RTD300: This application uses the LPSPI driver to transfer data with LPSPI2 (master, DMA) in a hardware loopback configuration (MOSI connected to MISO).
• Example codes provided with the RTDs.

BR, VaneB

[il_ciancio]

Hi @VaneB,

attached you will find my project:

• I have connected LPSPI0 (slave) and LPSPI2 (master);
• LPSPI2 is working with DMA;
• LPSPI0 is working without DMA;

running the code, I see that the data sent by LPSPI2 is received by LPSPI0, but the data sent by LPSPI0 is NOT received by LPSPI2.

Moreover, If I try to sent again data the code goes to in an HardFaultHandler.

Do you have any idea?

[il_ciancio]

The hard faul handler was raised becaus of a typo error on line 220 of main.c:
Lpspi_Ip_AsyncTransmit(&MASTER_EXTERNAL_DEVICE, TxMasterBuffer, RxMasterBuffer, NUMBER_OF_BYTES, TIMEOUT);

I have changed TIMEOUT with a callback, but the data are not exchanged between the LSPI.

Thanks and sorry for the error.